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| m68hc08 microcontrollers freescale.com mc68hc908lb8 data sheet mc68hc908lb8 rev. 0 2/2005
mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 3 mc68hc908lb8 data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://www.freescale.com the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) 2 2 /2005 0 first release n/a mc68hc908lb8 data sheet, rev. 0 4 freescale semiconductor mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 5 list of sections chapter 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 chapter 2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 chapter 3 analog-to-digital converter ( adc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 chapter 4 op amp/comparator module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 chapter 5 configuration regist er (config) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 chapter 6 computer operat ing properly (cop) module . . . . . . . . . . . . . . . . . . . . . . . . . 61 chapter 7 central processor unit (cpu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 chapter 8 external interrupt (i rq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 chapter 9 keyboard interrupt m odule (kbi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 chapter 10 high resolution pwm (hrp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 chapter 11 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 chapter 12 low-voltage inhibit (l vi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 chapter 13 oscillator module (osc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 chapter 14 input/output (i/o) ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 chapter 15 pulse width modul ator with fault input (p wm) . . . . . . . . . . . . . . . . . . . . . . 139 chapter 16 resets and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 chapter 17 system integrati on module (sim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 chapter 18 timer interface module (tim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 chapter 19 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 chapter 20 electrical speci fications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 chapter 21 ordering information and mechanical specificat ions . . . . . . . . . . . . . . . . . 229 mc68hc908lb8 data sheet 6 freescale semiconductor mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 7 table of contents chapter 1 general description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2.1 standard features of the mc68hc908lb8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2.2 features of the cpu08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.6 pin function priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.7 system clock distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 chapter 2 memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4 register section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.5 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6 flash memory (flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.6.1 flash control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.6.2 flash page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.6.3 flash mass erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.6.4 flash program/read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.6.5 flash block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.6.6 flash block protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.6.7 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.6.8 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 chapter 3 analog-to-digital converter (adc) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.3.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.4 conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.3.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.4 monotonicity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 mc68hc908lb8 data sheet 8 freescale semiconductor 3.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.8.1 adc status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.8.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.8.3 adc clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 chapter 4 op amp/comparator module 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.6 op amp/comparator control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 chapter 5 configuration register (config) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 chapter 6 computer operating properly (cop) module 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.3 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.1 busclkx4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.2 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.3 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.4 internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.5 reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.6 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.3.7 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.4 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.6 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 mc68hc908lb8 data sheet freescale semiconductor 9 chapter 7 central processor unit (cpu) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 chapter 8 external interrupt (irq) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.4 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.6 irq status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 chapter 9 keyboard interrupt module (kbi) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 9.4 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.6 keyboard module during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.7.1 keyboard status and control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.7.2 keyboard interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 chapter 10 high resolution pwm (hrp) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 mc68hc908lb8 data sheet 10 freescale semiconductor 10.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.4.1 the principle of frequency dithering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 10.4.2 frequency dithering on the hrp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 10.4.3 duty cycle dithering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.4.4 frequency generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.4.5 variable frequency mode (hrpmode = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.4.6 variable duty cycle mode (hrpmode = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.4.7 dithering controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 10.4.8 dithering controller tim ebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.4.9 deadtime insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.7 hrp during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.7.1 input/output signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.8 hrp registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.8.1 hrp control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.8.2 hrp duty cycle registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.8.3 hrp period registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.8.4 hrp deadtime register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 10.8.5 frequency dithering hrp timebase registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 10.8.6 frequency dithering control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 10.9 hrp programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 chapter 11 low-power modes 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.1.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.1.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.2 analog-to-digital converter (adc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.2.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.2.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.3 break module (brk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.3.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.3.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.4 central processor unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.4.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.4.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.5 computer operating properly module (cop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.6 external interrupt module (irq). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.7 keyboard interrupt module (kbi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 mc68hc908lb8 data sheet freescale semiconductor 11 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.8 high resolution pwm (hrp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.9 low-voltage inhibit module (lvi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.9.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.9.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.10 op amp/comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.10.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.10.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.11 oscillator module (osc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.11.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.11.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.12 pulse-width modulator module (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.12.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.12.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.13 timer interface module (tim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.13.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.13.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.14 exiting wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.15 exiting stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 chapter 12 low-voltage inhibit (lvi) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 12.3.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12.3.2 forced reset operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12.3.3 voltage hysteresis protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 12.4 lvi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.5 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 chapter 13 oscillator module (osc) 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 13.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 13.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 13.3.1 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13.3.1.1 internal oscillator trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.3.1.2 internal to external clock switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13.3.2 external oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 mc68hc908lb8 data sheet 12 freescale semiconductor 13.3.3 xtal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.3.4 rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 13.4 oscillator module signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 26 13.4.2 crystal amplifier output pin (osc2/ptc1/busclkx4) . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.4.3 oscillator enable signal (simoscen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.4.4 xtal oscillator clock (xtalclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.4.5 rc oscillator clock (rcclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 26 13.4.6 internal oscillator clock (intclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 27 13.4.7 oscillator out 2 (busclkx4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 27 13.4.8 oscillator out (busclkx2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.6 oscillator during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.7 config2 options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.8 input/output (i/o) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.8.1 oscillator status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.8.2 oscillator trim register (osctrim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 chapter 14 input/output (i/o) ports 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 14.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 14.2.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 14.2.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 14.2.3 port a input pullup enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 14.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 14.3.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 14.3.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 14.4 port c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 14.4.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 14.4.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 14.4.3 port c input pullup enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 chapter 15 pulse width modulator with fault input (pwm) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 15.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 15.3 timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 15.3.1 resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 15.3.2 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 15.4 pwm generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 15.4.1 load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 15.4.2 pwm data overflow and underflow conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 15.4.3 output polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 15.5 fault protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 mc68hc908lb8 data sheet freescale semiconductor 13 15.5.1 fault condition input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 15.5.1.1 automatic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 15.5.1.2 manual mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15.5.2 software output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15.6 initialization and the pwmen bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 15.7 pwm operation in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 15.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 15.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 15.8 control logic block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 15.8.1 pwm counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 15.8.2 pwm counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 15.8.3 pwmx value registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 15.8.4 pwm control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 15.8.5 pwm control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 15.8.6 pwm disable mapping write-once register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 15.8.7 fault control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 15.8.8 fault status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 15.8.9 fault control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 15.9 pwm glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 chapter 16 resets and interrupts 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.2 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.2.1 effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.2.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.2.3 internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.2.3.1 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16.2.3.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 16.2.3.3 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 62 16.2.3.4 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 16.2.3.5 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 16.2.4 system integration module (sim) reset status register. . . . . . . . . . . . . . . . . . . . . . . . . . 163 16.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 16.3.1 effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 16.3.2 sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 16.3.2.1 software interrupt (swi) instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 16.3.2.2 break interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.3.2.3 irq pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.3.2.4 timer interface module (tim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 68 16.3.2.5 kbd0?kbd6 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.3.2.6 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.3.2.7 pulse-width modulator with fault input (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.3.2.8 high resolution pwm (hrp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 mc68hc908lb8 data sheet 14 freescale semiconductor chapter 17 system integrati on module (sim) 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 17.2 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 17.2.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 17.2.2 clock start-up from por. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 17.2.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 17.3 reset and system initializat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 17.3.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 17.3.2 active resets from intern al sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 17.3.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 17.3.2.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 17.3.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 17.3.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 17.3.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 74 17.3.2.6 monitor mode entry module reset (modrst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 17.4 sim counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 17.4.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 17.4.2 sim counter during stop mode recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 17.4.3 sim counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 17.5 exception control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 17.5.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 17.5.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 17.5.1.2 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 17.5.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 17.5.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 17.5.4 status flag protection in break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 17.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 17.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 17.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 17.7 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 17.7.1 break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 17.7.2 sim reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 17.7.3 break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 chapter 18 timer interface module (tim) 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 18.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 18.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 18.3.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 18.3.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 18.3.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 18.3.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 18.3.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 89 18.3.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 18.3.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 mc68hc908lb8 data sheet freescale semiconductor 15 18.3.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 18.3.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 18.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 18.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 18.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 18.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 18.6 tim during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 18.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 18.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 18.8.1 tim status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 93 18.8.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 18.8.3 tim counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 18.8.4 tim channel status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 18.8.5 tim channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 chapter 19 development support 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 19.2 break module (brk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 19.2.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 19.2.1.1 flag protection during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 19.2.1.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 03 19.2.1.3 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 19.2.1.4 cop during break in terrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 03 19.2.2 break module registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 19.2.2.1 break status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 19.2.2.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 19.2.2.3 break auxiliary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 19.2.2.4 break status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 19.2.2.5 break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 19.2.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 19.3 monitor module (mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 19.3.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 19.3.1.1 normal monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 19.3.1.2 forced monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 19.3.1.3 monitor vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 19.3.1.4 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19.3.1.5 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19.3.1.6 baud rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19.3.1.7 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19.3.2 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 chapter 20 electrical specifications 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 20.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 20.3 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 mc68hc908lb8 data sheet 16 freescale semiconductor 20.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 20.5 5.0-volt electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 20.6 5.0-volt control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 20.7 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 20.8 5.0-volt adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 20.9 op amp parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 20.10 comparator parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 20.11 timer interface module characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 20.12 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 chapter 21 ordering information and m echanical specifications 21.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 21.2 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 21.3 20-pin small outline integrated circuit (soic) package ? case #751d . . . . . . . . . . . . . . . . 230 21.4 20-pin plastic dual in-line package (pdip) ? case #738. . . . . . . . . . . . . . . . . . . . . . . . . . . 230 mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 17 chapter 1 general description 1.1 introduction the mc68hc908lb8 is a member of the low-cos t, high-performance m68hc08 family of 8-bit microcontroller units (mcus). all mcus in the fa mily use the enhanced m68hc 08 central processor unit (cpu08) and are available with a variety of modules , memory sizes, memory types, and package types. the mc68hc908lb8 has peripherals dedicated to hi gh resolution pwm and power factor correction (pfc). 1.2 features for convenience, features have been organized to reflect: standard features of the mc68hc908lb8 features of the cpu08 1.2.1 standard featur es of the mc68hc908lb8 features of the mc68hc908lb8 include: 8-mhz internal bus frequency trimmable internal oscillator: ? 4.0 mhz internal bus operation ? 8-bit trim capability ? 25% untrimmed ?5% trimmed 8 kbytes of 10 k write/erase cycle typical on-chip in application programmable flash memory with security option (1) 128 bytes of on-chip random-access memory (ram) dual channel high resolution pwm with dead time insertion and shutdown input. the outputs use frequency dithering to achieve a 4 ns output resolution. dual channel pulse-width modulator (pwm) modul e to provide power factor correction capability seven channel, 8-bit succes sive approximation analog-to-digital converter (adc) op amp/comparator for power factor corre ction capability or general purpose use 7-bit keyboard interrupt one 16-bit, 2-channel timer interface module with one output available on port pin (pta6) for input capture and pwm 17 general-purpose input/output (i/o) pins and one input only pin ? three shared with high resolution pwm (hrp) ? three shared with pwm module 1. no security feature is absolutely secu re. however, freescale semiconductor?s stra tegy is to make reading or copying the flash difficult for unauthorized users. general description mc68hc908lb8 data sheet, rev. 0 18 freescale semiconductor ? three shared with op amp/comparator ? seven shared with adc module (ad[0:6]) ? one shared with timer channel 0 ? two shared with osc1 and osc2 ? one shared with reset ? seven shared with keyboard interrupt ? one input-only pin shared with external interrupt (irq) available packages: ? 20-pin small outline integrated chip (soic) package ? 20-pin plastic dual in-line package (pdip) on-chip programming firmware for use with hos t personal computer which does not require high voltage for entry system protection features: ? optional computer operating properly (cop) reset ? low-voltage reset ? illegal opcode detection with reset ? illegal address detection with reset low-power design; fully static with stop and wait modes standard low-power modes of operation: ? wait mode ? stop mode master reset pin and power-on reset (por) 674 bytes of flash programming routines read-only memory (rom) break module (brk) to allow single breakpoint setting during in-circuit debugging internal pullup on rst pin to reduce customer system cost mcu block diagram mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 19 selectable pullups on ports a and c ? selection on an individual port bit basis ? during output mode, pullups are disengaged high current 8-ma sink / 10-ma source capability on all port pins 1.2.2 features of the cpu08 features of the cpu08 include: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 general description mc68hc908lb8 data sheet, rev. 0 20 freescale semiconductor figure 1-1. mcu block diagram 1.4 pin assignments figure 1-2 illustrates the pin assignment s for the 20-pin soic package. m68hc08 cpu control and status user flash ? 8 kbytes user ram ? 128 bytes monitor rom ? 350 bytes user flash vector space ? 34 bytes ddrb portb ddrc portc internal bus pta6 (1) /ad5/tch0/kbi6 pta5 (1) /rst /kbi5 pta4 (1) /ad4/kbi4 pta3 (1) /ad3/kbi3 pta2 (1) /ad2/kbi2 pta1 (1) /ad1/kbi1 pta0 (1) /ad0/kbi0 ptb7/v out /ad6/fault (2) ptb6/v? ptb5/v+ ptb4/pwm1 ptb3/pwm0 ptb2/fault (2) ptb1/bot ptb0/top ptc1 (1) /osc2 ptc0 (1) /osc1 power v ss v dd ddra porta ptc2 (1) /shtdwn/irq flash programming oscillator cpu registers arithmetic/logic unit (alu) system integration module dual channel pwm module high resolution pwm module low-voltage inhibit module computer operating properly module 2-channel timer module 8-bit analog-to-digital converter module op amp/comparator module keyboard interrupt module module routines rom ? 674 bytes registers ? 64 bytes 1. pin contains integrated pullup device. 2. fault function switchable between pins ptb2 and ptb7. notes: pin functions mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 21 figure 1-2. 20-pin soic and pdip pin assignments 1.5 pin functions table 1-1 provides a description of the pin functions. table 1-1. pin functions pin name description input/output v dd power supply power v ss power supply ground power pta0 pta0 ? general purpose i/o port input/output kbi0 ? keyboard interrupt input 0 input adc0 ? a/d channel 0 input input pta1 pta1 ? general purpose i/o port input/output kbi1 ? keyboard interrupt input 1 input adc1 ? a/d channel 1 input input pta2 pta2 ? general purpose i/o port input/output kbi2 ? keyboard interrupt input 2 input adc2 ? a/d channel 2 input input pta3 pta3 ? general purpose i/o port input/output kbi3 ? keyboard interrupt input 3 input adc3 ? a/d channel 3 input input pta4 pta4 ? general purpose i/o port input/output kbi4 ? keyboard interrupt input 4 input adc4 ? a/d channel 4 input input pta5 pta5 ? general purpose i/o port input/output rst ? reset input, active low with internal pullup and schmitt trigger input kbi5 ? keyboard interrupt input 5 input 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v dd v ss ptc0/osc1 ptc1/osc2 ptc2/shtdwn/irq ptb0/top ptb1/bot ptb2/fault ptb3/pwm0 ptb4/pwm1 pta6/adc5/tch0/kbi6 pta5/rst /kbi5 pta4/adc4/kbi4 pta3/adc3/kbi3 pta2/adc2/kbi2 pta1/adc1/kbi1 pta0/adc0/kbi0 ptb7/v out /adc6/fault ptb6/v? ptb5/v+ general description mc68hc908lb8 data sheet, rev. 0 22 freescale semiconductor 1.6 pin function priority table 1-2 is meant to resolve the priority if multiple functions are enabled on a single pin. note upon reset all pins come up as input ports regardless of the priority table. pta6 pta6 ? general purpose i/o port input/output kbi6 ? keyboard interrupt input 6 input tch0 ? timer channel 0 i/o input/output adc5 ? a/d channel 5 input input ptb0 ptb0 ? general purpose i/o port input/output top ? high resolution pwm output output ptb1 ptb1 ? general purpose i/o port input/output bot ? high resolution pwm output output ptb2 ptb2 ? general purpose i/o port input/output fault ? high resolution pwm fault input (switchable between ptb2 and ptb7) input ptb3 ptb3 ? general purpose i/o port input/output pwm0 ? pulse-width modul ator output 0 output ptb4 ptb4 ? general purpose i/o port input/output pwm1 ? pulse-width modul ator output 1 output ptb5 ptb5 ? general purpose i/o port input/output v+ ? op amp/comparator input input ptb6 ptb6 ? general purpose i/o port input/output v? ? op amp/comparator input input ptb7 ptb7 ? general purpose i/o port input/output v out ? op amp/comparator output output adc6 ? a/d channel 6 input input fault ? high resolution pwm fault input (switchable between ptb2 and ptb7) input ptc0 ptc0 ? general purpose i/o port input/output osc1 ? xtal, rc, or external oscillator input input ptc1 ptc1 ? general purpose i/o port input/output osc2 ? xtal oscillator output (xtal option only) rc or internal oscillator output (osc2en = 1 in ptapue register) output output ptc2 ptc2 ? general purpose input port input shtdwn ? high resolution pwm input input irq ? external interrupt with programmable pullup and schmitt trigger input table 1-1. pin functions (continued) pin name description input/output pin function priority mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 23 note any unused inputs and i/o ports should be tied to an appropriate logic level (either v dd or v ss ). although the i/o ports of the mc68hc908lb8 do not require termination, termination is recommended to reduce the possibility of static damage. table 1-2. function priority in shared pins pin name highest-to-low est priority sequence pta0 adc0 general description mc68hc908lb8 data sheet, rev. 0 24 freescale semiconductor 1.7 system clock distribution figure 1-3. system clock distribution diagram some of the modules inside the mcu use different clock sources. figure 1-3 shows a simplified clock connection diagram. the osc supplies the clock sources: busclkx4 is the basic reference clock of the device. it is either: ? the external crystal oscillator ? an external clock source ? an external rc oscillator ? the internal oscillator pwm flash programming rom hrp cop tim adc kbi cpu flash ram mon rom osc busclkx4 busclkx4 busclkx2 busclk sim mux irc v dd xrc r ext mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 25 chapter 2 memory 2.1 introduction the cpu08 can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: system registers 8192 bytes of user flash memory 128 bytes of random-access memory (ram) 674 bytes of flash programming routines read-only memory (rom) 34 bytes of user-defined vectors 2.2 unimplemented memory locations accessing an unimplemented location can cause an illegal address reset. in the memory map ( figure 2-1 ) and in register figures in this document, unimplemented locations are shaded. 2.3 reserved memory locations accessing a reserved location can have unpredictable effects on microcontroller (mcu) operation. in the figure 2-1 and in register figures in this document, reserv ed locations are marked with the word reserved or with the letter r. 2.4 register section most of the control, status, and data registers ar e in the zero page area of $0000?$0058. additional i/o registers have these addresses: $fe00; break status register, bsr $fe01; sim reset status register, srsr $fe02; break auxiliary register, brkar $fe03; break flag control register, bfcr $fe04; interrupt status register 1, int1 $fe05; interrupt status register 2, int2 $fe06; reserved $fe07; reserved $fe08; flash control register, flcr $fe09; break address register high, brkh $fe0a; break address register low, brkl $fe0b; break status and control register, brkscr $fe0c; lvi status register, lvisr $ff7e; flash block protect register, flbpr memory mc68hc908lb8 data sheet, rev. 0 26 freescale semiconductor data registers are shown in figure 2-2 . table 2-1 is a list of vector locations. $0000 i/o registers $0058 $0059 unimplemented (1) $007f $0080 random-access memory 128 bytes $00ff $0100 unimplemented (1) $037d $037e flash programming routines rom 674 bytes $061f $0620 $deff unimplemented (1) $de00 flash memory 8192 bytes $fdff $fe00 break status register (bsr) $fe01 sim reset status register (srsr) $fe02 break auxiliary register (brkar) $fe03 break flag control register (bfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $fe06 reserved $fe07 reserved $fe08 flash control register (flcr) $fe09 break address register high (brkh) $fe0a break address register low (brkl) $fe0b break status and control register (brkscr) $fe0c lvi status register (lvisr) $fe0d $fe1f unimplemented figure 2-1. memory map register section mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 27 $fe20 monitor rom 350 bytes $ff7d $ff7e flash block protect register (flbpr) $ff7f $ffbf unimplemented $ffc0 internal oscillator trim value $ffc1 $ffdd unimplemented $ffde $ffff (2) flash vectors 34 bytes 1. attempts to execute code fr om addresses in these ranges will generate an illegal address reset. 2. $fff6?$fffd used for eight security bytes addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 132. read: pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 134. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 136. read: 00000ptc2 ptc1 ptc0 write: reset:00000000 $0003 reserved reserved $0004 data direction register a (ddra) see page 133. read: 0 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 135. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 = unimplemented r = reserved bold = buffered u = unaffected figure 2-2. control, status, and data registers (sheet 1 of 8) figure 2-1. memory map (continued) memory mc68hc908lb8 data sheet, rev. 0 28 freescale semiconductor $0006 data direction register c (ddrc) see page 137. read: 000000 ddrc1 ddrc0 write: reset:00000000 $0007 $000c unimplemented $000d port a input pullup enable register (ptapue) see page 134. read: pta6pue pta5pue pta4pue pta3pue pta2pue pta1pue pta0pue write: reset:00000000 $000e port c input pullup enable register (ptcpue) see page 138. read: osc2en 0000 ptcpue2 ptcpue1 ptcpue0 write: reset:00000000 $000f $0019 unimplemented $001a keyboard status and control register (intkbscr) see page 87. read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (intkbier) see page 88. read: kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $001d irq status and control register (intscr) see page 82. read: 0000irqf0 imask mode write: ack reset:00000000 $001e configuration register 2 (config2) (1) see page 58. read: irqpud irqen r oscopt1 oscopt0 00 rsten write: reset:00000000 (2) 1. one-time writable register after each reset. 2. rsten reset to 0 by a power-on reset (por) only. $001f configuration register 1 (config1) (1) see page 59. read: coprs lvistop lvirstd lvipwrd 0 ssrec stop copd write: reset:00000000 1. one-time writable register after reach reset. addr.register name bit 7654321bit 0 = unimplemented r = reserved bold = buffered u = unaffected figure 2-2. control, status, and data registers (sheet 2 of 8) register section mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 29 $0020 timer status and control register (tsc) see page 193. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 timer counter register high (tcnth) see page 194. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0022 timer counter register low (tcntl) see page 194. read: bit 7 654321bit 0 write: reset:00000000 $0023 timer counter modulo register high (tmodh) see page 195. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0024 timer counter modulo register low (tmodl) see page 195. read: bit 7654321bit 0 write: reset:11111111 $0025 timer channel 0 status and control register (tsc0) see page 196. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 timer channel 0 register high (tch0h) see page 199. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0027 timer channel 0 register low (tch0l) see page 199. read: bit 7654321bit 0 write: reset: indeterminate after reset $0028 timer channel 1 status and control register (tsc1) see page 196. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 timer channel 1 register high (tch1h) see page 199. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002a timer channel 1 register low (tch1l) see page 199. read: bit 7654321bit 0 write: reset: indeterminate after reset $002b $0029 unimplemented addr.register name bit 7654321bit 0 = unimplemented r = reserved bold = buffered u = unaffected figure 2-2. control, status, and data registers (sheet 3 of 8) memory mc68hc908lb8 data sheet, rev. 0 30 freescale semiconductor $0030 $0033 reserved reserved $0034 $0035 unimplemented $0036 oscillator status register (oscstat) see page 128. read: rrrrrrecgon eggst write: reset:00000000 $0037 unimplemented $0038 oscillator trim register (osctrim) see page 129. read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 $0039 op amp/comparator control register (oaccr) see page 55. read: oacm oace write: reset:0uuuuuu0 $003a $003b unimplemented $003c adc status and control register (adscr) see page 48. read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $003d unimplemented $003e adc data register (adr) see page 50. read: ad7 ad6 ad5 ad4 a3 ad2 ad1 ad0 write: reset: unaffected by reset $003f adc clock register (adclk) see page 50. read: adiv2 adiv1 adiv0 00000 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved bold = buffered u = unaffected figure 2-2. control, status, and data registers (sheet 4 of 8) register section mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 31 $0040 pwm control register 1 (pctl1) see page 153. read: 0 fpos pwmint pwmf 00 ldok pwmen write: reset:00000000 $0041 pwm control register 2 (pctl2) see page 155. read: ldfq1 ldfq0 dis1 dis0 pol1 pol0 prsc1 prsc0 write: reset:00001100 $0042 fault control register (fcr) see page 157. read: 000000 fint fmode write: reset:00000000 $0043 fault status register (fsr) see page 157. read: 000000fpinfflag write: reset:u0u0u0u0 $0044 fault control register 2 (fcr2) see page 158. read: 00000000 write: ftack reset:00000000 $0045 pwm counter register high (pcnth) see page 151. read: 0000bit 11bit 10bit 9bit 8 write: reset:00000000 $0046 pwm counter register low (pcntl) see page 151. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 $0047 pwm counter modulo register high (pmodh) see page 152. read: 0000 bit 11 bit 10 bit 9 bit 8 write: reset:0000 indeterminate after reset $0048 pwm counter modulo register low (pmodl) see page 152. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset: indeterminate after reset $0049 pwm 0 value register high (pval0h) see page 152. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 $004a pwm 0 value register low (pval0l) see page 153. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $004b pwm 1 value register high (pval1h) see page 152. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved bold = buffered u = unaffected figure 2-2. control, status, and data registers (sheet 5 of 8) memory mc68hc908lb8 data sheet, rev. 0 32 freescale semiconductor $004c pwm 1 value register low (pval1l) see page 153. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $004d pwm disable mapping write once register (dismap) see page 156. read: 000000 map1 map0 write: reset:00000011 $004e $004f unimplemented $0050 reserved reserved $0051 hrp control register (hrpctrl) see page 103. read: shtlvl hrpoe shtif shtie shten hrp- mode (1) hrpen write: reset 0000000 1. when hrpmode bit = 0, step[4:0] are mapped into the hrpperl register ? when hrpmode = 1, step[4:0] are ma pped into the hrpdcl register. $0052 hrp duty cycle register high (hrpdch) see page 105. read: dc10 dc9 dc8 dc7 dc6 dc5 dc4 dc3 write: reset00000000 $0053 hrp duty cycle register low (hrpdcl) see page 105. read: dc2 dc1 dc0 step4 step3 step3 step1 step0 write: reset00000000 $0054 hrp period register high (hrpperh) see page 105. read: p10p9p8p7p6p5p4p3 write: reset00000000 $0055 hrp period register low (hrpperl) see page 105. read: p2 p1 p0 step4 step3 step2 step1 step0 write: reset00000000 $0056 hrp dead time register (hrp_dt) see page 106. read: dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 write: reset00001000 $0057 hrp timebase register high (hrptbh) see page 106. read: tb15 tb14 tb13 tb12 tb11 tb10 tb9 tb8 write: reset00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved bold = buffered u = unaffected figure 2-2. control, status, and data registers (sheet 6 of 8) register section mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 33 $0058 hrp timebase register low (hrptbl) see page 106. read: tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 write: reset00000000 $0059 frequency dithering control register (hrpdcr) see page 107. read: clksrc sel2 sel1 sel0 write: reset 0000 $005a $005f reserved reserved $fe00 break status register (bsr) see page 181. read: rrrrrr sbsw r write: (note) reset:00000000 note: writing a 0 clears sbsw. $fe01 sim reset status register (srsr) see page 182. read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 $fe02 break auxiliary register (brkar) see page 204. read: bit 7 6 5 4 3 2 1 bit 0 write: reset:00000000 $fe03 break flag control register (bfcr) see page 183. read: bcferrrrrrr write: reset:00000000 $fe04 $fe07 reserved reserved $fe08 flash control register (flcr) see page 37. read: 0000 hven mass erase pgm write: reset:00000000 $fe09 break address register high (brkh) see page 204. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0a break address register low (brkl) see page 204. read: bit 7654321bit 0 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved bold = buffered u = unaffected figure 2-2. control, status, and data registers (sheet 7 of 8) memory mc68hc908lb8 data sheet, rev. 0 34 freescale semiconductor $fe0b break status and control register (brkscr) see page 203. read: brke brka 000000 write: reset:00000000 $fe0c lvi status register (lvisr) see page 119. read: lviout 0000000 write: reset:00000000 $ffc0 internal oscillator trim value tri m7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 factory programmed flash byte $ffc1 reserved reserved $ff7e flash block protect register (flbpr) (1) see page 42. read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: unaffected by reset 1. non-volatile flash register $ffff cop control register (copctl) see page 63. read: low byte of reset vector write: writing clears cop counter (any value) reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved bold = buffered u = unaffected figure 2-2. control, status, and data registers (sheet 8 of 8) random-access memory (ram) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 35 . 2.5 random-access memory (ram) addresses $0080 through $00ff are ram locations. t he location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64-kbyte memory space. table 2-1. vector addresses vector priority address vector highest lowest $ffff reset vector (low) $fffe reset vector (high) $fffd swi vector (low) $fffc swi vector (high) $fffb irq vector (low) $fffa irq vector (high) $fff9 memory mc68hc908lb8 data sheet, rev. 0 36 freescale semiconductor note for correct operation, the stack pointer must point only to ram locations. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. note for m6805 compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note be careful when using nested subrouti nes. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. 2.6 flash memory (flash) this section describes the operation of the em bedded flash memory. this memory can be read, programmed, and erased from a single external suppl y. the program, erase, and read operations are enabled through the use of an internal charge pump. it is recommended that the user utilize the flash programming routines provided in the on-chip rom, which are described more fully in a separate freescale semiconductor application note. the flash memory is an array of 8 kbytes with an additional 34 bytes of user vectors and one byte of block protection. an erased bit reads as 1 and a programmed bit reads as a 0 . memory in the flash array is organized into two rows per page basis. for the 8-k word by 8-bit embedded flash memory, the page size is 64 bytes per page and the row size is 32 bytes per row. hence the minimum erase page size is 64 bytes and the minimum program row size is 32 bytes. program and erase operations are facilitated through control bits in flash control register (flcr). details for these operations appear later in this section. the address ranges for the user memory and vectors are: $de00?$fdff; user memory $fe08 ; flash control register $ff7e; flash block protect register $ffde?$ffff; these locations are reserved for user-defined interrupt and reset vectors flash memory (flash) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 37 programming tools are available from freescale semiconductor. contact your local freescale semiconductor representative for more information. note a security feature prevents viewing of the flash contents. (1) 2.6.1 flash control register the flash control register (flcr) controls flash program and erase operations. hven ? high-voltage enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operations in the array. hven can only be set if either pgm = 1 or erase = 1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit setting this read/write bit configures the 8- kbyte flash array for mass erase operation. 1 = mass erase operation selected 0 = page erase operation selected erase ? erase control bit this read/write bit configures t he memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit configures the memory for progr am operation. pgm is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected 2.6.2 flash page erase operation use this step-by-step procedure to erase a page (64 bytes) of flash memory to read as logic 1. a page consists of 64 consecutive bytes starting from addr esses $xx00, $xx40, $xx80, or $xxc0. the 34-byte user interrupt vectors area also forms a page. any flash memory page can be erased alone, except for the 34-byte interrupt vectors page, which must be mass erased. 1. no security feature is absolutely secu re. however, freescale semiconductor?s stra tegy is to make reading or copying the flash difficult for unauthorized users. address: $fe08 bit 7654321bit 0 read:0000 hven mass erase pgm write: reset:00000000 = unimplemented figure 2-3. flash control register (flcr) memory mc68hc908lb8 data sheet, rev. 0 38 freescale semiconductor 1. set the erase bit, and clear the mass bit in the flash control register. 2. read the flash block protect register. 3. write any data to any flash location within the address range of the block to be erased. 4. wait for a time, t nvs (minimum 10 note programming and erasing of flash locations cannot be performed by code being executed from flash memo ry. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. caution be aware that erasing the vector page wi ll erase the internal oscillator trim value at $ffc0. it is highly recommended that interrupts be disabled during program/ erase operations. in applications that need more than 1000 program/er ase cycles, use the 4-ms page erase specification to get improved long-term reliability. any applicati on can use this 4-ms page erase specification. however, in applications where a flash location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1-ms page erase specification to get a shorter cycle time. 2.6.3 flash m ass erase operation use this step-by-step procedure to erase entire flash memory to read as logic 1: 1. set both the erase bit and the mass bit in the flash control register. 2. read from the flash block protect register. 3. write any data to any flash address (1) within the flash memory address range. 4. wait for a time, t nvs (minimum 10 note mass erase is disabled whenever any block is protected (flbpr does not equal $ff). 8. wait for a time, t nvhl (minimum 100 flash memory (flash) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 39 9. clear the hven bit. 10. after time, t rcv (typical 1 note programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. caution a mass erase will erase the intern al oscillator trim value at $ffc0. 2.6.4 flash progra m/read operation programming of the flash memory is done on a row basis. a row consists of 32 consecutive bytes starting from addresses $xx00, $xx20, $xx40, $xx60, $xx80, $xxa0, $xxc0, and $xxe0. during the programming cycle, make sure that all addr esses being written to fit within one of the ranges specified above. attempts to program addresses in different row ranges in one programming cycle will fail. use this step-by-step procedure to program a row of flash memory ( figure 2-4 is a flowchart representation). note in order to avoid program disturbs, the row must be erased before any byte on that row is programmed. 1. set the pgm bit. this configures the memory for program operation and enables the latching of address and data for programming. 2. read from the flash block protect register. 3. write any data to any flash address within the row address range desired. 4. wait for a time, t nvs (minimum 10 note the cop register at location $ffff should not be written between steps 5-12, when the hven bit is set. since this register is located at a valid flash address, unpredictable behavior may occur if this location is written while hven is set. this program sequence is repeated throughout the memory until all data is programmed. 1. the time between each flash address ch ange, or the time between the last fl ash address programmed to clearing pgm bit, must not exceed the maximum programming time, t prog maximum. memory mc68hc908lb8 data sheet, rev. 0 40 freescale semiconductor note programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. do not exceed t prog maximum, see 20.12 memory characteristics . it is highly recommended that interrupts be disabled during program/erase operations. do not exceed t prog maximum or t hv maximum. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvx = t nvh + t pgs + (t prog x 32) <= t hv maximum refer to 20.12 memory characteristics . the time between programming the flash address change (step 7 to step 7), or the time between the last flash programmed to clearing the pgm bit (st ep 7 to step 10) must not exceed the maximum programming time, t prog maximum. caution be cautious when programming the flash array to ensure that non-flash locations are not used as the address that is written to when selecting either the desired row address range in step 3 of the algorithm or the byte to be programmed in step 7 of the algorithm. this applies particularly to $ffd4?$ffdf. 2.6.5 flash bl ock protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made for protecting a bloc k of memory from unintentional erase or program operations due to system malfunction. this protection is done by using of a flash block protect register (flbpr). the flbpr determines the range of the flash memory which is to be protected. the range of the protected area starts from a location defined by flbpr and ends at the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or program operations. note in performing a program or erase operation, the flash block protect register must be read after setting the pgm or erase bit and before asserting the hven bit when the flbpr is program with all 0?s, the entir e memory is protected from being programmed and erased. when all the bits are erased (all 1?s), the entire memory is accessible for program and erase. when bits within the flbpr are programmed, they lock a block of memory, address ranges as shown in 2.6.6 flash block protect register . once the flbpr is programmed with a value other than $ff, any erase or program of the flbpr or the protected bloc k of flash memory is prohibited. the presence of a v tst on the irq pin will bypass the block protection so that all of the memory included in the block protect register is open for program and erase operations. note the flash block protect register is not protected with special hardware or software. therefore, if this page is not protected by flbpr the register is erased by either a page or mass erase operation. flash memory (flash) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 41 figure 2-4. flash programming flowchart set hven bit write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash address change (step 7 to step 7), must not exceed the maximum programming time, t prog max. or the time between the last flash address programmed to clearing pgm bit (step 7 to step 10) notes: 1 3 4 5 6 7 8 10 11 12 13 algorithm for programming a row (32 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased. 9 read the flash block protect register 2 memory mc68hc908lb8 data sheet, rev. 0 42 freescale semiconductor 2.6.6 flash bloc k protect register the flash block protect register (flbpr) is impl emented as a byte within the flash memory, and therefore can only be written during a programming sequence of the flash memory. the value in this register determines the starting location of the protected range within the flash memory. bpr[7:0] ? flash block protect bits these eight bits represent bits [13:6] of a 16-bit memory address. bit 15 and 14 are 1s and bits [5:0] are 0s. the resultant 16-bit address is used for specifying the start address of the flash memory for block protection. the flash is protected from this star t address to the end of flash memory, at $ffff. with this mechanism, the protec t start address can be $xx00, $xx40, $xx80, and $xxc0 (64 bytes page boundaries) within the flash memory. figure 2-6. flash block protect start address address: $ff7e bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:uuuuuuuu u = unaffected by reset. initial value from factory is 1. write to this register is by a programming sequence to the flash memory. figure 2-5. flash block protect register (flbpr) table 2-2. examples of protect address ranges bpr[7:0] addresses of protect range $00?$78 the entire flash memory is protected. $79 ( 0111 1001 )$de40 (11 01 1110 01 00 0000) ? $ffff $7a ( 0111 1010 )$de80 (11 01 1110 10 00 0000) ? $ffff $7b ( 0111 1011 ) $dec0 (11 01 1110 11 00 0000) ? $ffff $7c ( 0111 1100 )$df00 (11 01 1111 00 00 0000) ? $ffff and so on... $fc ( 1111 1100 )$ff00 (11 11 1111 00 00 0000) ? ffff $fd ( 1111 1101 ) $ff40 (11 11 1111 01 00 0000) ? $ffff flbpr and vectors are protected $fe ( 1111 1110 ) $ff80 (1 111 1111 10 00 0000) ? ffff vectors are protected $ff the entire flash memory is not protected. 1 flbpr value 16-bit memory address 000000 start address of flash 1 block protect flash memory (flash) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 43 2.6.7 wait mode putting the mcu into wait mode while the flash is in read mode does not affect the operation of the flash memory directly, but there will not be any memory activity since the cpu is inactive. the wait instruction should not be executed while performing a program or erase operation on the flash, otherwise the operation will discontinue, and the flash will be on standby mode. 2.6.8 stop mode putting the mcu into stop mode while the flash is in read mode does not affect the operation of the flash memory directly, but there will not be any memory activity since the cpu is inactive. the stop instruction should not be executed while performing a program or erase operation on the flash, otherwise the operation will discontinue, and the flash will be on standby mode note standby mode is the power saving mode of the flash module in which all internal control signals to the flash are inactive and the current consumption of the flash is at a minimum. memory mc68hc908lb8 data sheet, rev. 0 44 freescale semiconductor mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 45 chapter 3 analog-to-digital converter (adc) 3.1 introduction this section describes the 8-bit analog-to-digital converter (adc). figure 3-1. block diagram highlighting adc block and pins m68hc08 cpu control and status user flash ? 8 kbytes user ram ? 128 bytes monitor rom ? 350 bytes user flash vector space ? 34 bytes ddrb portb ddrc portc internal bus pta6 (1) /ad5/tch0/kbi6 pta5 (1) /rst /kbi5 pta4 (1) /ad4/kbi4 pta3 (1) /ad3/kbi3 pta2 (1) /ad2/kbi2 pta1 (1) /ad1/kbi1 pta0 (1) /ad0/kbi0 ptb7/v out /ad6/fault (2) ptb6/v? ptb5/v+ ptb4/pwm1 ptb3/pwm0 ptb2/fault (2) ptb1/bot ptb0/top ptc1 (1) /osc2 ptc0 (1) /osc1 power v ss v dd ddra porta ptc2 (1) /shtdwn/irq flash programming oscillator cpu registers arithmetic/logic unit (alu) system integration module dual channel pwm module high resolution pwm module low-voltage inhibit module computer operating properly module 2-channel timer module 8-bit analog-to-digital converter module op amp/comparator module keyboard interrupt module module routines rom ? 674 bytes registers ? 64 bytes 1. pin contains integrated pullup device. 2. fault function switchable between pins ptb2 and ptb7. notes: analog-to-digital converter (adc) mc68hc908lb8 data sheet, rev. 0 46 freescale semiconductor 3.2 features features of the adc module include: 7 channels with multiplexed input linear successive approximation 8-bit resolution single or continuous conversion conversion complete flag or conversion complete interrupt selectable adc clock 3.3 functional description seven adc channels are available for sampling ex ternal sources at pins ptb7/adc6, pta6/adc5, pta4/adc4?pta0/adc0. an analog multiplexer allows a single adc converter to select one of seven adc channels as adc voltage in (adcvin). adcvin is converted by the successive approximation register based counters. when the conversion is complete , adc places the result in the adc data register and sets a flag or generates an interrupt. see figure 3-2 . figure 3-2. adc block diagram 3.3.1 adc port i/o pins ptb7/adc6, pta6/adc5, pta4/adc4?pta0/adc0 are general-purpose i/o (input/output) pins that share with the adc channels. the channel select bits define which adc channel/port pin will be used as internal data bus read ddrax/ddrbx write ddrax/ddrbx reset write ptax/ptbx read ptax/ptbx ptax/ptbx ddrax/ddrax ptax/ptbx interrupt logic channel select adc clock generator conversion complete adc (v adin ) adc clock bus clock adch[4:0] adc data register aien coco disable disable adc channel x adiv[2:0] voltage in monotonicity mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 47 the input signal. the adc overrides the port i/o logic by forcing that pin as input to the adc. the remaining adc channels/port pins are controlle d by the port i/o logic and can be used as general-purpose i/o. writes to the port register or data direction r egister (ddr) will not have any effect on the port pin that is selected by the adc. read of a port pin in use by the adc will return a logic 0. if the ddr bit is at 1, the value in the port data latch is read. 3.3.2 voltage conversion when the input voltage to the adc equals v refh , the adc converts the signal to $ff (full scale). if the input voltage equals v refl , the adc converts it to $00. input voltages between v refh and v refl are a straight-line linear conversion. v refh and v refl are internally connected to v dd and v ss respectively. 3.3.3 conversion time conversion starts after a write to the adc status and control register (adscr). one conversion will take between 16 and 17 adc clock cycles. the adivx bit should be set to provide a 1-mhz adc clock frequency. 3.3.4 conversion in continuous conversion mode, the adc data register will be filled with new data after each conversion. data from the previous conversion will be over written whether that data has been read or not. conversions will conti nue until the adco bit is cleared. the coco bit is set after the first conversion and will stay set until the next write of the adc status and control register or the next read of the adc data register. in single conversion mode, conversion begins with a write to t he adscr. only one conversion occurs between writes to the adscr. 3.3.5 accuracy and precision the conversion process is monot onic and has no missing codes. 3.4 monotonicity the conversion process is monot onic and has no missing codes. 3.5 interrupts when the aien bit is set, the adc module is c apable of generating cpu interrupts after each adc conversion. a cpu interrupt is generated if the co co bit is at 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. 16 to 17 adc cycles adc frequency conversion time = number of bus cycles = conversion time analog-to-digital converter (adc) mc68hc908lb8 data sheet, rev. 0 48 freescale semiconductor 3.6 low-power modes the wait and stop instruction can put the mcu in low power consumption standby modes. 3.6.1 wait mode the adc continues normal operation du ring wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting ad ch4?adch0 bits in the adc status and control register before executing the wait instruction. 3.6.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc functionality resume when the mcu exits stop mode after an external interrupt. allow one conversion cycle to stabilize the analog circuitry. 3.7 i/o signals the adc module has seven pins shared wi th ports a and b: ptb7/adc6, pta6/adc5, pta4/adc4?pta0/adc0. v adin is the input voltage signal from one of the seven adc channels to the adc module. 3.8 i/o registers these i/o registers control and monitor adc operation: adc status and control register (adscr) adc data register (adr) adc clock register (adclk) 3.8.1 adc status and control register function of the adc status and control register (adscr) is described here. coco ? conversions complete bit when the aien bit is a 0, the coco is a read-only bi t which is set each time a conversion is completed except in the continuous c onversion mode where it is set after the first conversion. this bit is cleared whenever the adscr is written or whenever the adr is read. if the aien bit is a 1, the coco becomes a read/write bit, which should be cleared to 0 for cpu to service the adc interrupt request. reset clears this bit. address: $003c bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 figure 3-3. adc status and control register (adscr) i/o registers mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 49 1 = conversion completed (aien = 0) 0 = conversion not completed (aien = 0)/cpu interrupt (aien = 1) aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at th e end of an adc conversion. the interrupt signal is cleared when the data register is read or the status/control register is written. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ? adc continuous conversion bit when set, the adc will convert samples continuously and update the adr register at the end of each conversion. only one conversion is completed between writes to the adscr when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch4?adch0 ? adc channel select bits adch4?adch0 form a 5-bit field which is used to se lect one of 7 adc channels. only seven channels, ad6?ad0, are available on this mcu. the channels are detailed in table 3-1 . care should be taken when using a port pin as both an analog and digita l input simultaneously to prevent switching noise from corrupting the analog signal. see table 3-1 . the adc subsystem is turned off when the channel select bits are all set to 1. this feature allows for reduced power consumption for the mcu when the adc is not being used. note recovery from the disabled state requi res one conversion cycle to stabilize. the voltage levels supplied from internal reference nodes, as specified in table 3-1 , are used to verify the operation of the adc converter both in production test and for user applications. table 3-1. mux channel select (1) adch4 adch3 adch2 adch1 adch0 input select 00000 pta0/ad0 00001 pta1/ad1 00010 pta2/ad2 00011 pta3/ad3 00100 pta4/ad4 00101 pta6/ad5 00110 ptb7/ad6 01000 unused analog-to-digital converter (adc) mc68hc908lb8 data sheet, rev. 0 50 freescale semiconductor 3.8.2 adc data register one 8-bit result register is provided. this regist er is updated each time an adc conversion completes. 3.8.3 adc clock register the adc clock register (adclk) selects the clock frequency for the adc. adiv2?adiv0 ? adc clock prescaler bits adiv2?adiv0 form a 3-bit field which selects the divi de ratio used by the adc to generate the internal adc clock. table 3-2 shows the available clock configurat ions. the adc clock should be set to approximately 1 mhz. notes: 1. if any unused channels are selected, the resulting adc conv ersion will be unknown or re- served. 2. v refh and v refl are internally connected to v dd and v ss respectively. address: $003e read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: unaffected by reset = unimplemented figure 3-4. adc data register (adr) address: $003f bit 7654321bit 0 read: adiv2 adiv1 adiv0 00000 write: reset:00000000 = unimplemented figure 3-5. adc clock register (adclk) table 3-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock i/o registers mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 51 the adc requires a clock rate of approximately 1 mhz for correct operation. if the selected clock source is not fast enough, the adc will generate incorrect conversions. see 20.8 5.0-volt adc characteristics . f adic = bus frequency adiv[2:0] ? analog-to-digital converter (adc) mc68hc908lb8 data sheet, rev. 0 52 freescale semiconductor mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 53 chapter 4 op amp/comparator module 4.1 introduction this section describes the functionality of the op amp/comparator. 4.2 features features of the op amp/comparator include: software enable/disable op amp and comparator modes for optimized performance shared output pin with adc input pin and pwm faul t pin to allow a op amp/ comparator circuit to be inputs to these modules 4.3 pin name conventions the op amp/comparator shares two input pins and an out put pin with the port b input/output (i/o). the full names of the op amp/comparator pins are listed in table 4-1 . note that the generic pin names appear in the text that follows. table 4-1. pin name conventions generic pin name full pin name v out ptb7/v out/ adc6/fault v? ptb6/v? v+ ptb5/v+ op amp/comparator module mc68hc908lb8 data sheet, rev. 0 54 freescale semiconductor figure 4-1. block diagram highlighting op amp/comparator block and pins 4.4 functional description the op amp/comparator module has two modes of ope ration ? op amp mode and comparator mode. op amp mode optimizes the module for accurate signal amplification with low input offset voltage. comparator mode optimizes the module for use as a comparator with fast output response. the output of the op amp/comparator shares its pin with an analog-to-digital converter (adc6) channel. the fault function of the pwm can also be switched to share this pin. the adc channel function and the op amp output can be enabled simultaneously so that the output of the op amp could be sampled directly by the associated adc channels. see figure 4-2. note setting an op amp/comparator enable control bit (oace) and an op amp/comparator module selected contro l bit (oacm) forces v+ and v? to be inputs and v out to be an output, overriding the data direction register. m68hc08 cpu control and status user flash ? 8 kbytes user ram ? 128 bytes monitor rom ? 350 bytes user flash vector space ? 34 bytes ddrb portb ddrc portc internal bus pta6 (1) /ad5/tch0/kbi6 pta5 (1) /rst /kbi5 pta4 (1) /ad4/kbi4 pta3 (1) /ad3/kbi3 pta2 (1) /ad2/kbi2 pta1 (1) /ad1/kbi1 pta0 (1) /ad0/kbi0 ptb7/v out /ad6/fault (2) ptb6/v? ptb5/v+ ptb4/pwm1 ptb3/pwm0 ptb2/fault (2) ptb1/bot ptb0/top ptc1 (1) /osc2 ptc0 (1) /osc1 power v ss v dd ddra porta ptc2 (1) /shtdwn/irq flash programming oscillator cpu registers arithmetic/logic unit (alu) system integration module dual channel pwm module high resolution pwm module low-voltage inhibit module computer operating properly module 2-channel timer module 8-bit analog-to-digital converter module op amp/comparator module keyboard interrupt module module routines rom ? 674 bytes registers ? 64 bytes 1. pin contains integrated pullup device. 2. fault function switchable between pins ptb2 and ptb7. notes: low power modes mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 55 in order to read the digital states of the pins configured as inputs, the data direction register bit must be a 0; to read the states of the pins configured as outputs the data direction register bit must be a 1. figure 4-2. op amp/comparator block diagram 4.5 low power modes 4.5.1 wait mode the wait instruction places the mcu in a low power consumption mode. while in wait the op amp/comparator cannot be enabled or disabled. if the op amp/comparator module is not needed during wait mode, reduce power consumption by disabli ng the op amp/comparator before executing the wait command. 4.5.2 stop mode the op amp/comparator is inactive afte r execution of the stop command. the op amp/comparator will be in a low-power state and w ill not drive its output pin. when the mcu exits stop mode after and external interrupt, the op amp/comparator continues operation. 4.6 op amp/comparator control register there is a single operational control register (oaccr) that contains the enable bit for the op amp/comparator. oacm ? op amp/comparator mode select bit this bit selects between 2 modes of operation, op amp mode and comparator mode. 1 = op amp mode selected address: $0039 bit 7654321bit 0 read: oacm oace write: reset:0uuuuuu0 = unimplemented u = unaffected figure 4-3. op amp/comparator control register (oaccr) + - v out ground v+ oace ground v? oace oace floating oace op amp/comparator module mc68hc908lb8 data sheet, rev. 0 56 freescale semiconductor 0 = comparator mode selected oace ? op amp/comparator enable bit setting of the corresponding bit in the register enables the associated op amp/comparator and connects it to the op amp/comparator pins. 1 = op amp/comparator is connected to pins and powered on 0 = op amp/comparator is disconnected from pins and powered off note enabling the op amp/comparator prevents ptb[5:7] from being used as standard i/o. however, the ptb7 pin can be shared with ad6 and fault if the adc and pwm modules are also enabled. mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 57 chapter 5 configuration register (config) 5.1 introduction this section describes the configuration registers, config1 and config2. the configuration registers enable or disable these options: cop timeout period (2 18 ? 2 4 or 2 13 ? 2 4 busclkx4 cycles) stop instruction stop mode recovery (32 x busclkx4 cycles or 4096 x busclkx4 cycles) computer operating properly module (cop) low-voltage inhibit (lvi) module control irq pin rst pin osc option selection 5.2 functional description the configuration registers are used in the initializatio n of various options. the c onfiguration registers can be written once after each reset. all of the configurat ion register bits are cleared during reset. since the various options affect the operation of the microcontroller unit (mcu), it is recommended that these registers be written immediately after reset. the conf iguration registers are located at $001e and $001f and may be read at anytime. note on a flash device, the options are one-time writable by the user after each reset. the config registers are not in the flash memory but are special registers containing one-time writable latches after each reset. upon a reset, the config registers default to predetermined settings as shown in figure 5-1 and figure 5-2 . configuration register (config) mc68hc908lb8 data sheet, rev. 0 58 freescale semiconductor irqpud ? irq pin pullup control bit 1 = internal pullup is disconnected 0 = internal pullup is connected between pin irq and v dd irqen ? irq pin function selection bit 1 = interrupt request function active in pin 0 = interrupt request function inactive in pin oscopt1 and oscpot0 ? selection bits for oscillator option rsten ? rst pin function selection 1 = reset function active in pin 0 = reset function inactive in pin note the rsten bit is cleared by a power-on reset (por) only. other resets will leave this bit unaffected. address: $001e bit 7654321bit 0 read: irqpud irqen r oscopt1 oscopt0 00 rsten write: reset:0000000u por:00000000 = unimplemented r = reserved u = unaffected figure 5-1. configuration register 2 (config2) oscopt[1:0] oscillator selection 00 internal oscillator 01 external oscillator 10 external rc oscillator 11 external xtal oscillator functional description mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 59 coprs ? cop rate select bit copd selects the cop timeout period. reset clears coprs. see chapter 6 computer operating properly (cop) module 1 = cop timeout period = 2 13 ? 2 4 busclkx4 cycles 0 = cop timeout period = 2 18 ? 2 4 busclkx4 cycles lvistop ? lvi enable in stop mode bit when the lvipwrd bit is clear, setting the lvisto p bit enables the lvi to operate during stop mode. reset clears lvistop. 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode lvirstd ? lvi reset disable bit lvirstd disables the reset si gnal from the lvi module. see chapter 12 low-voltage inhibit (lvi) . 1 = lvi module resets disabled 0 = lvi module resets enabled lvipwrd ? lvi power disable bit lvipwrd disables the lvi module. see chapter 12 low-voltage inhibit (lvi) . 1 = lvi module power disabled 0 = lvi module power enabled ssrec ? short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 32 busclkx4 cycles instead of a 4096-busclkx4 cycle delay. 1 = stop mode recovery after 32 busclkx4 cycles 0 = stop mode recovery after 4096 busclkx4 cycles note exiting stop mode by an lvi reset will result in the long stop recovery. if running with external crystal, it is advisable to set the short stop recovery bit to 0. the short stop recovery does not provide enough time for oscillat or stabilization and for this reason the ssrec bit should not be set. when using the lvi during normal operation but disabling during stop mode, the lvi will have an enable time of t en . the system stabilization time for power-on reset and long stop recovery (both 4096 busclkx4 cycles) gives a delay longer than the lv i enable time for these startup scenarios. there is no period where the mcu is not protected from a low-power condition. however, when using the short stop recovery configuration option, the 32-bu sclkx4 delay must be greater than the lvi?s turn on time to avoid a period in startup where the lvi is not protecting the mcu. address: $001f bit 7654321bit 0 read: coprs lvistop lvirstd lvipwrd 0 ssrec stop copd write: reset:00000000 = unimplemented figure 5-2. configuration register 1 (config1) configuration register (config) mc68hc908lb8 data sheet, rev. 0 60 freescale semiconductor stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit copd disables the cop module. see chapter 6 computer operating properly (cop) module . 1 = cop module disabled 0 = cop module enabled mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 61 chapter 6 computer operating pr operly (cop) module 6.1 introduction the computer operating properly (cop) module cont ains a free-running counter that generates a reset if allowed to overflow. the cop modul e helps software recover from runaway code. prevent a cop reset by clearing the cop counter periodically. the cop m odule can be disabled through the copd bit in the configuration 1 (config1) register. 6.2 functional description figure 6-1. cop block diagram copctl write busclkx4 reset vector fetch sim reset circuit reset status register internal reset sources (1) sim module clear stages 5?12 12-bit sim counter clear all stages copd (from config1) reset copctl write clear cop module copen (from sim) cop counter 1. see chapter 17 system integration module (sim) for more details. cop clock cop timeout cop rate select (coprs from config1) 6-bit cop counter computer operating properly (cop) module mc68hc908lb8 data sheet, rev. 0 62 freescale semiconductor the cop counter is a free-running 6-bit counter prec eded by the 12-bit system integration module (sim) counter. if not cleared by software, the cop counter overflows and generates an asynchronous reset after 2 18 ?2 4 or 2 13 ?2 4 busclkx4 cycles; depending on the state of the cop rate select bit, coprs, in configuration register 1. with a 2 18 ?2 4 busclkx4 cycle overflow option, using the internal clock to produce bus speed of 4 mhz gives a cop timeout period of 16.383 ms. writing any value to location $ffff before an overflow occurs prevents a cop re set by clearing the cop counter and stages 12?5 of the sim counter. note service the cop immediately after rese t and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. a cop reset pulls the rst pin low for 32 note place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt s ubroutine could keep the cop from generating a reset even while the main program is not working properly. 6.3 i/o signals the following paragraphs describe the signals shown in figure 6-1 . 6.3.1 busclkx4 busclkx4 is the oscillator outpu t signal. busclkx4 frequency is equal to the crystal frequency, the internal oscillator frequency, or the rc oscillator frequency. 6.3.2 copctl write writing any value to the cop control register (copctl) (see 6.4 cop control register ) clears the cop counter and clears bits 12?5 of the sim counter. reading the cop control register returns the low byte of the reset vector. 6.3.3 powe r-on reset the power-on reset (por) circuit in the sim clears the sim counter 4096 cop control register mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 63 6.3.6 copd (cop disable) the copd signal reflects the state of the cop dis able bit (copd) in the configuration register 1 (config1). see chapter 5 configuration register (config) . 6.3.7 coprs (cop rate select) the coprs signal reflects the state of the cop rate select bit (coprs) in the configuration register 1 (config1). see chapter 5 configuration register (config) . 6.4 cop control register the cop control register (copctl) is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and star ts a new timeout period. reading location $ffff returns the low byte of the reset vector. 6.5 interrupts the cop does not generate cpu interrupt requests. 6.6 monitor mode the cop is disabled in monitor mode when v tst is present on the irq pin. 6.7 low-power modes the wait and stop instructions put the microcontroller unit (mcu) in low power-consumption standby modes. 6.7.1 wait mode the cop remains active during wait mode. if cop is enabled, a reset will occur at cop timeout. 6.7.2 stop mode stop mode turns off the busclkx4 input to the cop and clears the sim counter. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. to prevent inadvertently turning off the cop with a stop instruction, a configuration option is available that disables the stop instruction. when the stop bit in the configuration register has the stop instruction disabled, execution of a stop in struction results in an illegal opcode reset. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 6-2. cop control register (copctl) computer operating properly (cop) module mc68hc908lb8 data sheet, rev. 0 64 freescale semiconductor mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 65 chapter 7 central processor unit (cpu) 7.1 introduction the m68hc08 cpu (central processor unit) is an e nhanced and fully object-code- compatible version of the m68hc05 cpu. the cpu08 reference manual (freescale semiconductor document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 7.2 features features of the cpu include: object code fully upward-compatible with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-re gister manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes low-power stop and wait modes 7.3 cpu registers figure 7-1 shows the five cpu registers. cpu registers are not part of the memory map. central processor unit (cpu) mc68hc908lb8 data sheet, rev. 0 66 freescale semiconductor figure 7-1. cpu registers 7.3.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. 7.3.2 index register the 16-bit index register allows i ndexed addressing of a 64-kbyte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, th e cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. bit 7654321bit 0 read: write: reset: unaffected by reset figure 7-2. accumulator (a) bit 151413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 7-3. index register (h:x) accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 cpu registers mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 67 7.3.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset a ddressing modes, the stack pointer can function as an index register to access data on t he stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note the location of the stack is arbitrary and may be relocated anywhere in random-access memory (ram). moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. 7.3.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increm ents to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. 7.3.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set per manently to 1. the following paragraphs describe the functions of the condition code register. bit 151413121110987654321 bit 0 read: write: reset:0000000011111111 figure 7-4. stack pointer (sp) bit 151413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 7-5. program counter (pc) central processor unit (cpu) mc68hc908lb8 data sheet, rev. 0 68 freescale semiconductor v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. th e daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask when the interrupt mask is set, all maskable cp u interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note to maintain m6805 family compatibil ity, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priori ty interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 7-6. condition code register (ccr) arithmetic/logic unit (alu) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 69 c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 7.4 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (freescale semiconductor document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 7.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 7.5.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains cl ear. after exit by reset, the i bit is set. disables the cpu clock 7.5.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the conditi on code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins ru nning after the oscillator stabilization delay. 7.6 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted. central processor unit (cpu) mc68hc908lb8 data sheet, rev. 0 70 freescale semiconductor 7.7 instruction set summary table 7-1 provides a summary of the m68hc08 instruction set. table 7-1. instruction set summary (sheet 1 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a ? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a ? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ?? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc ) = 0 instruction set summary mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 71 bgt opr branch if greater than (signed operands) pc ) = 0 ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc ) = ) = dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 table 7-1. instruction set summary (sheet 2 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) mc68hc908lb8 data sheet, rev. 0 72 freescale semiconductor bset n , opr set bit n in m mn ?? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ?? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ?? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a instruction set summary mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 73 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( ) ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ?? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 table 7-1. instruction set summary (sheet 4 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 central processor unit (cpu) mc68hc908lb8 data sheet, rev. 0 74 freescale semiconductor lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ??0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a ?? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp ( ) ( ) ( ) ?? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ?? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp inh 80 7 rts return from subroutine sp ; ( instruction set summary mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 75 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a ?? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) ? dir 35 dd 4 stop enable interrupts, stop processing, refer to mcu documentation i ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a ?? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc inh 84 2 tax transfer a to x x ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x central processor unit (cpu) mc68hc908lb8 data sheet, rev. 0 76 freescale semiconductor 7.8 opcode map see table 7-2 . wait enable interrupts; wait for interrupt i bit set or cleared n negative bit ? not affected table 7-1. instruction set summary (sheet 7 of 7) source form operation description effect on ccr address mode opcode operand cycles vh i nzc table 7-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1 2 3 4 5 6 9e6 7 8 9 a b c d 9ed e 9ee f 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4 sp2 3 sub 2ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4 sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4 sp2 3 cmp 2ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4 sp2 3 sbc 2ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3 sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4 sp2 3 cpx 2ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4 sp2 3 and 2ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4 sp2 3 bit 2ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4 sp2 3 lda 2ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4 sp2 3 sta 2ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4 sp2 3 eor 2ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4 sp2 3 adc 2ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4 sp2 3 ora 2ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4 sp2 3 add 2ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4 sp2 3 ldx 2ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4 sp2 3 stx 2ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb central processor unit (cpu) mc68hc908lb8 data sheet, rev. 0 78 freescale semiconductor mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 79 chapter 8 external interrupt (irq) 8.1 introduction the irq (external interrupt) module provides a maskable interrupt input. 8.2 features features of the irq module include: a multiplexed external interrupt pin (irq ) irq interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge selectable internal pullup resistor 8.3 functional description irq pin functionality is enabled by setting configurati on register 2 (config2) irqen bit accordingly. a zero disables the irq function and irq will assume the other shared functionalities. a one enables the irq function. a logic 0 applied to the external interrupt pin can latch a central processor unit (cpu) interrupt request. figure 8-1 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until one of the following actions occurs: vector fetch ? a vector fetch automatically gener ates an interrupt acknowledge signal that clears the latch that caused the vector fetch. software clear ? software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (intscr). writing a 1 to the ack bit clears the irq latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is falling-edge triggered and is software-configurable to be either falling-edge or falling-edge and low-level triggered. the mode bit in the intscr controls the triggering sensitivity of the irq pin. when an interrupt pin is edge-triggered only, the interrupt remains set until a vector fetch, software clear, or reset occurs. external interrupt (irq) mc68hc908lb8 data sheet, rev. 0 80 freescale semiconductor figure 8-1. irq module block diagram when an interrupt pin is both falling-edge and low-level triggered, the interrupt remains set until both of these events occur: vector fetch or software clear return of the interrupt pin to logic 1 the vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. as long as the pin is low, the interrupt request remains pending. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. when set, the imask bit in the intscr masks all external interrupt requests. a latched interrupt request is not presented to the interrupt priori ty logic unless the imask bit is clear. note the interrupt mask (i) in the condi tion code register (ccr) masks all interrupt requests, including external interrupt requests. 8.4 irq pin a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. addr.register name bit 7654321bit 0 $001d irq status and control register (intscr) see page 82. read:0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 8-2. irq i/o register summary ack imask dq ck clr irq high interrupt to mode select logic irq ff request v dd mode voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd internal pullup device irq irqpud irq module during break interrupts mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 81 if the mode bit is set, the irq pin is both falling-edge-sensitive a nd low-level-sensitive. with mode set, both of the following actions must occur to clear irq: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a 1 to the ack bit in the interrupt status and control register (intscr). t he ack bit is useful in applications that poll the irq pin and require software to clear the irq latch. writing to the ack bit prior to leaving an interrupt service routine can also prevent spur ious interrupts due to noise. setting ack does not affect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack bit latches another interrupt request. if the irq mask bit, imask, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. return of the irq pin to logic 1 ? as long as the irq pin is at logic 0, irq remains active. the vector fetch or software clear and the return of the irq pin to logic 1 may occur in any order. the interrupt request remains pending as long as the irq pin is at logic 0. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge-sensitive only. with mode clear, a vector fetch or software clear immediately clears the irq latch. the irqf bit in the intscr register can be used to check for pending interrupts. the irqf bit is not affected by the imask bit, which makes it usef ul in applications where polling is preferred. use the bih or bil instruction to read the logic level on the irq pin. note if the irq function is not enabled for pin ptc2/shtdwn/irq, bil and bih instructions will always read a logic 1 value. when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. an internal pullup resistor to v dd is connected to the irq pin; this can be disabled by setting the irqpud bit in the config2 register ($001e). 8.5 irq module duri ng break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear the latch during the break state. see 19.2 break module (brk) . to allow software to clear the irq latch during a break interrupt, write a 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect cpu interrupt flags during the break state, wr ite a 0 to the bcfe bit. with bcfe at 0 (its default state), writing to the ack bit in the irq status and control register during the break state has no effect on the irq interrupt flags. 8.6 irq status and control register the irq status and control register (intscr) contro ls and monitors operation of the irq module. the intscr: shows the state of the irq flag clears the irq latch masks irq interrupt request external interrupt (irq) mc68hc908lb8 data sheet, rev. 0 82 freescale semiconductor controls triggering sensitivity of the irq interrupt pin irqf ? irq flag bit this read-only status bit is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending ack ? irq interrupt request acknowledge bit writing a 1 to this write-only bit clears the irq latch. ack always reads as 0. reset clears ack. imask ? irq interrupt mask bit writing a 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt requests on falling edges only address: $001d bit 7654321bit 0 read: irqf 0 imask mode write: ack reset:00000000 = unimplemented figure 8-3. irq status and control register (intscr) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 83 chapter 9 keyboard interrupt module (kbi) 9.1 introduction the keyboard interrupt module (kbi) provides sev en independently maskable external interrupts which are accessible via pta0?pta6. when a port pin is enabl ed for keyboard interrupt function, an internal pullup device is also enabled on the pin. figure 9-1. block diagram highlighting kbi block and pins m68hc08 cpu control and status user flash ? 8 kbytes user ram ? 128 bytes monitor rom ? 350 bytes user flash vector space ? 34 bytes ddrb portb ddrc portc internal bus pta6 (1) /ad5/tch0/kbi6 pta5 (1) /rst /kbi5 pta4 (1) /ad4/kbi4 pta3 (1) /ad3/kbi3 pta2 (1) /ad2/kbi2 pta1 (1) /ad1/kbi1 pta0 (1) /ad0/kbi0 ptb7/v out /ad6/fault (2) ptb6/v? ptb5/v+ ptb4/pwm1 ptb3/pwm0 ptb2/fault (2) ptb1/bot ptb0/top ptc1 (1) /osc2 ptc0 (1) /osc1 power v ss v dd ddra porta ptc2 (1) /shtdwn/irq flash programming oscillator cpu registers arithmetic/logic unit (alu) system integration module dual channel pwm module high resolution pwm module low-voltage inhibit module computer operating properly module 2-channel timer module 8-bit analog-to-digital converter module op amp/comparator module keyboard interrupt module module routines rom ? 674 bytes registers ? 64 bytes 1. pin contains integrated pullup device. 2. fault function switchable between pins ptb2 and ptb7. notes: keyboard interrupt module (kbi) mc68hc908lb8 data sheet, rev. 0 84 freescale semiconductor 9.2 features features include: seven keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask hysteresis buffers programmable edge-only or edge- and level- interrupt sensitivity exit from low-power modes i/o (input/output) port bit(s) software configurable with pullup device(s) if configured as input port bit(s) figure 9-2. keyboard module block diagram addr.register name bit 7654321bit 0 $001a keyboard status and control register (intkbscr) see page 87. read:0000 keyf 0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (intkbier) see page 88. read: kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 9-3. i/o register summary kbie0 kbie6 . . . keyboard interrupt dq ck clr v dd modek imaskk request vector fetch decoder ackk internal bus reset to pullup enable kbi6 kbi0 to pullup enable synchronizer keyf functional description mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 85 9.3 functional description writing to the kbie6?kbie0 bits in the keyboard interrupt enable register independently enables or disables each port a pin as a keyboard interrupt pi n. enabling a keyboard interrupt pin also enables its internal pullup device. a logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched when one or more keyboard pins goes low after all were high. the modek bit in the keyboard status and control regi ster controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. to prevent losing an interrupt request on one pin because another pin is still low, softwar e can disable the latter pin while it is low. if the keyboard interrupt is falling edge- and low-level sensitive, an interrupt request is present as long as any keyboard interrupt pin is low and the pin is keyboard interrupt enabled. if the modek bit is set, the keyboard interrupt pins are both falling edge- and low-level sensitive, and both of the following actions must occur to clear a keyboard interrupt request: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software may generate the inte rrupt acknowledge signal by writing a 1 to the ackk bit in the keyboard status and control regi ster (intkbscr). the ackk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that oc curs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the cpu loads the program counter with the vector address at locations $ffe0 and $ffe1. return of all enabled keyboard interrupt pins to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. with modek clear, a vector fetch or software clear immediately clears the keyboard interrupt request. reset clears the keyboard interrupt request and the mo dek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the keyboard status and control register can be used to see if a pending interrupt exists. the keyf bit is not affected by t he keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. note setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a 0 for software to read the pin. keyboard interrupt module (kbi) mc68hc908lb8 data sheet, rev. 0 86 freescale semiconductor 9.4 keyboard initialization when a keyboard interrupt pin is enabled, it takes time fo r the internal pullup to reach a logic 1. therefore, a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edge-triggered pin can be acknowledged immediately a fter enabling the pin. an interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. another way to avoid a false interrupt: 1. configure the keyboard pins as outputs by setti ng the appropriate ddra bits in data direction register a. 2. write 1s to the appropriate port a data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 9.5 low-power modes the wait and stop instructions put the microcontroller unit (mcu) in low power-consumption standby modes. 9.5.1 wait mode the keyboard module remains active in wait mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. 9.5.2 stop mode the keyboard module remain s active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. 9.6 keyboard module during break interrupts the system integration module (sim) controls whet her the keyboard interrupt latch can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. to allow software to clear the keyboard interrupt latch during a break interrupt, write a 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latch during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), writing to the keyboard acknowledge bit (ackk) in t he keyboard status and control register during the break state has no effect. see 9.7.1 keyboard status and control register . i/o registers mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 87 9.7 i/o registers these registers control and monitor operation of the keyboard module: keyboard status and control register (intkbscr) keyboard interrupt enable register (intkbier) 9.7.1 keyboard status and contro l register the keyboard status and control register: flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard interrupt triggering sensitivity bits 7?4 ? not used these read-only bits always read as 0s. keyf ? keyboard flag bit this read-only bit is set when a keyboard inte rrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a 1 to this write-only bit clears the keyboard interrupt request. ackk always reads as 0. reset clears ackk. imaskk ? keyboard interrupt mask bit writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only 9.7.2 keyboard inte rrupt enable register the keyboard interrupt enable register enables or disables each port a pin to operate as a keyboard interrupt pin. address: $001a bit 7654321bit 0 read:0000keyf0 imaskk modek write: ackk reset:00000000 = unimplemented figure 9-4. keyboard status and control register (intkbscr) keyboard interrupt module (kbi) mc68hc908lb8 data sheet, rev. 0 88 freescale semiconductor kbie6?kbie0 ? keyboard interrupt enable bits each of these read/write bits enables the corre sponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = ptax pin enabled as keyboard interrupt pin 0 = ptax pin not enabled as keyboard interrupt pin address: $001b bit 7654321bit 0 read: kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 figure 9-5. keyboard interrupt enable register (intkbier) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 89 chapter 10 high resolution pwm (hrp) 10.1 introduction the high resolution pwm (hrp) provides two complementary outputs that can be used to control half-bridge systems in, for example, light ballast applic ations. it uses a dithering control method to provide a high step resolution (3.906 ns from an 8 mhz input cl ock). it also provides a s hutdown input that can be used to disable the outputs when a fault condition is detected in the application. the pins supporting the hrp can be seen in figure 10-1 , and a block diagram of the hrp module is shown in figure 10-3 . 10.2 features features of the hrp include: one complementary output pair for driving a half bridge dithering between two frequencies or duty cycles, for increased output resolution automatic calculation of second fre quency or duty cycle for output dithering variable frequency mode with automatic 50% duty cycle calculation variable duty cycle mode programmable deadtime insertion shutdown input for fast disabling of outputs 10.3 pin name conventions the hrp shares two output pins with two port b input/ output (i/o) pins and one input pin with one port c input pin. table 10-1. pin naming conventions hrp generic pin name full hrp pin name top ptb0/top bot ptb1/bot shtdwn ptc2/shtdwn/irq high resolution pwm (hrp) mc68hc908lb8 data sheet, rev. 0 90 freescale semiconductor figure 10-1. block diagram highlighting hrp block and pins note setting the hrpoe bit in the hrpctrl register forces the corresponding hrp output pins to be outputs, overriding the data direction register. in order to read the states of the pins, the data direction register bit must be a0. setting the shten bit in the hrpctrl register forces the shtdwn pin to be an input, overriding the data direction register. in order to read the state of the pin, the data direction register bit must be a 0. m68hc08 cpu control and status user flash ? 8 kbytes user ram ? 128 bytes monitor rom ? 350 bytes user flash vector space ? 34 bytes ddrb portb ddrc portc internal bus pta6 (1) /ad5/tch0/kbi6 pta5 (1) /rst /kbi5 pta4 (1) /ad4/kbi4 pta3 (1) /ad3/kbi3 pta2 (1) /ad2/kbi2 pta1 (1) /ad1/kbi1 pta0 (1) /ad0/kbi0 ptb7/v out /ad6/fault (2) ptb6/v? ptb5/v+ ptb4/pwm1 ptb3/pwm0 ptb2/fault (2) ptb1/bot ptb0/top ptc1 (1) /osc2 ptc0 (1) /osc1 power v ss v dd ddra porta ptc2 (1) /shtdwn/irq flash programming oscillator cpu registers arithmetic/logic unit (alu) system integration module dual channel pwm module high resolution pwm module low-voltage inhibit module computer operating properly module 2-channel timer module 8-bit analog-to-digital converter module op amp/comparator module keyboard interrupt module module routines rom ? 674 bytes registers ? 64 bytes 1. pin contains integrated pullup device. 2. fault function switchable between pins ptb2 and ptb7. notes: functional description mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 91 note when hrpmode = 0, step[4:0] are mapped into the five least significant bits of the hrpperl register. when hrpmode = 1, step[4:0] are mapped into the five least significant bits of the hrpdcl register. 10.4 functional description figure 10-3 provides a block diagram of the module. addr.register name bit 7654321bit 0 $0051 hrp control register (hrpctrl) see page 103. read: shtlvl hrpoe shtif shtie shten hrpmode hrpen write: reset 0000000 $0052 hrp duty cycle register high (hrpdch) see page 105. read: dc10 dc9 dc8 dc7 dc6 dc5 dc4 dc3 write: reset00000000 $0053 hrp duty cycle register low (hrpdcl) see page 105. read: dc2 dc1 dc0 step4 step3 step3 step1 step0 write: reset00000000 $0054 hrp period register high (hrpperh) see page 105. read: p10p9p8p7p6p5p4p3 write: reset00000000 $0055 hrp period register low (hrpperl) see page 105. read: p2 p1 p0 step4 step3 step2 step1 step0 write: reset00000000 $0056 hrp deadtime register (hrpdt) see page 106. read: dt7dt6dt5dt4dt3dt2dt1dt0 write: reset00001000 $0057 hrp timebase register high (hrptbh) see page 106. read: tb15 tb14 tb13 tb12 tb11 tb10 tb9 tb8 write: reset00000000 $0058 hrp timebase register low (hrptbl) see page 106. read: tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 write: reset00000000 $0059 frequency dithering control register (hrpdcr) see page 107. read: clksrc sel2 sel1 sel0 write: reset 0000 = unimplemented figure 10-2. hrp i/o register summary high resolution pwm (hrp) mc68hc908lb8 data sheet, rev. 0 92 freescale semiconductor figure 10-3. block diagram of high resolution pwm (hrp) the hrp comprises four blocks, as follows 1. a dual frequency generator, which generates a pair of complementary pwm output signals. it allows dithering between two adjacent frequencies or duty cycles to increase the resolution of the output signal. after deadtime insertion, these signals are routed to the top and bot output pins 2. a dithering controller, or timebase, which sets t he dithering cycle time and the percentage of time spent on each of the dithering frequencies or duty cycles. 3. two deadtime generators, for inserting deadtime into the output signals. 4. a set of control registers the hrp can operate in two modes. 1. variable frequency mode: for variation of the output frequency at a fixed 50% duty cycle 2. variable duty cycle mode: for variation of the duty cycle at a fixed frequency. 10.4.1 the principle of frequency dithering frequency dithering is an averaging technique, which ca n increase the resolution of an output signal by switching between two frequencies. by varying the ti me spent on each frequency, the average output frequency will be a value between the two frequencies. for example, in figure 10-4 a signal switches between 10 khz and 20 khz over a fixed cycle time. 30% of each cycle is spent at 20 khz, 70% at 10 khz. the equivalent average frequency over time is 13 khz. dithering controller dual frequency generator deadtime generator deadtime generator complementary outputs with programmable deadtime shutdown detect input for fast disabling of outputs top bot shtdwn control registers internal bus busclk hrpclk functional description mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 93 figure 10-4. dithering waveforms 10.4.2 frequency dit hering on the hrp the hrp provides frequency dithering between two si gnals whose periods differ by one hrpclk cycle. when the hrp is supplied with an 8 mhz clock, the difference between the period values is 125 ns. the hrp provides a programmable number of dithering steps, up to a maximum of 32 steps. this results in a maximum frequency resolution of 125/32 = 3.906 ns when using an 8 mhz clock. figure 10-5 shows the relationship between the two dithering frequencies and the output frequency when 32 dithering steps are chosen. in this example, the pe riod signal is output for 25% of the time, i.e. 8 of the 32 steps, and the period+1 signal is output for 75% of the time, i.e. 24 of the 32 steps. 10 060 50 40 30 20 70 80 90 100 10 khz 20 khz 1 cycle 20 khz 10 khz average signal 13 khz % cycle t high resolution pwm (hrp) mc68hc908lb8 data sheet, rev. 0 94 freescale semiconductor figure 10-5. high resolution pwm dithering 10.4.3 duty cycle dithering as an alternative to frequency dithering, duty cycle di thering, where dithering occurs between two signals having the same frequency, but with duty cycles di ffering by one clock period. the hrp can perform duty cycle dithering with the same step resolution as the frequency dithering opti on (125/32 = 3.906 ns, with an 8 mhz clock). 10.4.4 frequency generation the dual frequency generator block contains a 16-bit up counter, which generates an output signal, based on the values in the period register hrpperh:hr pperl and the duty cycle register hrpdch:hrpdcl. the output signal and its inverse are later fed into the deadtime generators for deadtime insertion. multiplexors on the inputs of the period register and the duty cycle register select between two period (period1 and period2) and two duty cycle (duty1 and duty2) values. the values of period1, period2, duty1, and duty2 are determined by the hrpmode bit in the hrpctrl register and the contents of the hrpperh:hrpperl and hrpdch:hrpdcl registers. period1 and duty1 define the frequency output by the dual-frequency generator; period2 and duty2 define a second output frequency, which is automatically calculated by the hrp module. the module switches between period1/duty1 and period2/duty2. t period +1 = $81 period = $80 frequency = 1/ ($81 * 125 ns) = 62.015 khz frequency = 1/ ($80 * 125 ns) = 62.500 khz steps 08 16 24 period = $80 period +1 = $81 average frequency = 62.015 + (( 62.500 ? 62.015 ) /32 * 8 ) = 62.136 khz 0 16 24 80 functional description mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 95 the rate of switching is controlled by the dither ing controller, and is dependent on the values of the clksrc bit and the sel[2:0] bits in the hrpdcr register, the contents of the hrptbh:hrptbl registers, and, depending on the val ue of the hrpmode bit, the five leas t significant bits in the hrpperl or hrpdcl registers . for more detailed information, see 10.4.7 dithering controller . table 10-2. hrpmode bit options hrpmode mode period1 period2 duty1 duty2 0 variable frequency p[10:0] p[10:0] +1 period1/2 period2/2 1 variable duty cycle p[10:0] p[10:0] dc[10:0] dc[10:0] +1 figure 10-6. dithering controller and dual frequency generator block hrptbh hrptbl compare 16-bit counter divider compare compare modulus 5-bit counter s r q frequency duty cycle register up counter period register dc[10:0] p[10:0] hrpmode dual frequency generator dithering timebase +1 /2 /2 to deadtime generators select 10 01 10 01 10 reset hrpclk +1 duty 1 duty 2 period 1 period 2 step[4:0] sel[2:0] 0 1 increment clk src clksel = 0, clock from dual frequency generator clksel = 1, clock from 16-bit timebase counter functional description mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 97 10.4.5 variable fr equency mode (hrpmode = 0) variable frequency mode is selected when hrpmode = 0 . in this mode the period of the output signal can be varied, while keeping the duty cycle fixed at 50%. period1, period2, duty1, and duty2 are calculated from bits p[10:0] in registers hrpperh:hrpperl to produce two frequencies having periods differing by one clock cycle but both with 50% duty cycles. table 10-2 lists the period and duty cycle va lues based on the hrpmode bit. the scaled value in step[4:0] (the five least significant bits of hrpperh:hrpperl) specifies how many of the selected number of steps are spent on the longer period (period2). for more detailed information, see 10.4.7 dithering controller . the formula for calculating the average output period in variable frequency mode (including dithering) is: (eq 10-1) where the function int() represents the integer part of the operand, and 2 sel[2:0] is the step[4:0] scaling factor. in variable frequency mode, the individual periods and duty cycles are given by: (eq 10-2) (eq 10-3) (eq 10-4) (eq 10-5) 10.4.6 variable duty cycle mode (hrpmode = 1) variable duty cycle mode is selected when hrpmode = 1. this mode allows dithering to be achieved by varying the duty cycle of the output wave form while keeping the period fixed. in this mode, the period of both period1 and perio d2 are identical. duty2 is automatically set to duty1 + 1. this provides two signals with the same frequency but with duty cycles differing by one bus clock cycle. dithering between these two signals can in crease the resolution of the output by a factor of up to 32. the scaled value in step[4: 0] (the five least signi ficant bits of hrpdch:hrpdcl) specifies how many of the selected number of steps are spent on the longer duty cycle, duty2. for more detailed information, see 10.4.7 dithering controller . output period (seconds) p10:0 [] [] ?? ?? 5 9 period2 p[10:0] 1 + hrpclk -------------------------- - = duty2 period2 2 ------------------------- - 50% duty cycle = = high resolution pwm (hrp) mc68hc908lb8 data sheet, rev. 0 98 freescale semiconductor the formula for calculating the output du ty cycle in variable duty cycle mode is: (eq 10-6) where 2 sel[2:0] is the step[4:0] scaling factor. in variable duty cycle mode, the individual periods and duty cycles are given by: (eq 10-7) (eq 10-8) (eq 10-9) (eq 10-10) 10.4.7 dithering controller the dithering controller consists of a 5-bit counter with programmable modulus. the counter contents are compared with a scaled version of the step[4:0] bits. the modulus value (i.e., the total number of steps) and the step[4:0] scaling factor are set by the sel bits in the hrp configuration register. table 10-3 lists the available options. note that the scaling of the step[4:0] bits is linked to the modul us value. for example, if a modulus of 32 is chosen, step[4:0] is not scaled (32 steps of dithering are available). if a modul us of 16 is chosen, step[4:0] is divided by 2, so that only 16 steps of dithering are available. for example, if you decide to have 16 steps (sel = 1) instead of the maximum of 32, and you set step[4:0] equal to 23, then the scaled value of step will be 11 (i.e., the integer part of 23 divided by 2). if you decide to have 4 steps instead of 32, the scaled value of 23 would be 2 (the integer part of 23 divided by 8). table 10-3. number of steps and step scaling sel number of steps divide step[4:0] by... 0 32 1 1 16 2 2 8 4 3 4 8 4 2 16 5 0 32 6 reserved reserved 7 reserved reserved output duty cycle dc 10:0 [] [] ?? ?? functional description mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 99 step[4:0] is read from register hrpperl (if hrpmod e = 0) or from register hrpdcl (if hrpmode = 1). see 10.4.4 frequency generation for more detailed information on the hrpmode bit. thus, by varying the value of step[4:0], the programmer can vary the output signal. 10.4.8 dithering controller timebase the 5-bit counter may be clocked from the dual fr equency generator counter or from a 16-bit timebase. the clock source is selected by the clksrc bit in the hrpdcr register. clocking from the dual frequency generator sets the ti mebase for each dithering step equal to the period of the hrp output waveform. clocking from the 16-bit timebase allows longer or s horter timebases to be used. this allows the system designer to set the switching frequency to a certain value, to avoid undesirable harmonics or beat frequencies. table 10-4 shows the clock options a nd corresponding timebase values. 10.4.9 deadtime insertion the deadtime generators receive the two output signal s top and bot from the dual frequency generator block. deadtime is incorporated into these signals on eac h positive edge by delaying the positive edge for a number of clock cycles. the number of clock cycles is equal to the value in the 8-bit hrp deadtime register hrpdt. figure 10-7 shows the relationship between the top and bot input signals to the deadtime generators, the hrpdt register contents, and the outputs from the deadtime generators. table 10-4. dithering timebase options clksel clock source timebase 0 dual frequency generator 1 16 bit timebase p(10:0) hrpclk ------------------------- - hrptbh:hrptbl hrpclk ------------------------------------------------- - high resolution pwm (hrp) mc68hc908lb8 data sheet, rev. 0 100 freescale semiconductor figure 10-7. deadtime insertion waveforms note care must be taken when setting the duty cycle and deadtime values to ensure that a pwm signal appears on both top and bot when using the module to control a half bridge. it is possible to configure the hrp to output a continuous logic 0 on top or bot. if the deadtime is equal to or greater than the duty cycle value, the bot output will will remain at logic 0, while top will output a pwm signal. (see figure 10-8 .) similarly, if the deadtime is equal to or smaller than the period minus the duty cycle value, the top output will re main at logic 0, while bot will output a pwm signal. (see figure 10-9 .) dt[7:0] dt[7:0] top in bot in top out bot out functional description mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 101 figure 10-8. deadtime equal to or greater than duty cycle figure 10-9. deadtime equal to or less than period minus duty cycle deadtime deadtime 16 16 0 step coun t 16 16 deadtime deadtime top bot duty cycle = 5 duty cycle = 4 period = 16, deadtime = 4 16 deadtime deadtime 16 0 16 16 16 step coun t deadtime deadtime duty cycle = 11 duty cycle = 12 top bot period = 16, deadtime = 4 16 high resolution pwm (hrp) mc68hc908lb8 data sheet, rev. 0 102 freescale semiconductor 10.5 interrupts setting bits shtie and shten shtif in the hrp cont rol register (hrpctrl) configures the shtdwn input to generate a cpu interrupt on detection of a falling edge or a low-level on the shtdwn pin. the interrupt remains set until both of these events occur: the interrupt flag, shtif, is cleared. shtif is cleared by writing a logic 0 to bit shtif in the hrpctrl register. return of the shtdwn pin to logic 1 note while the shtdwn pin remains low, the interrupt request remains pending. 10.6 low-power modes 10.6.1 wait mode the wait instruction puts the mcu in low power consumption standby mode. the hrp remains active after the execution of a wait instruction. in wait m ode, the hrp registers are not accessible by the cpu. any enabled cpu interrupt request from the hrp can bring the mcu out of wait mode. if hrp functions are not required during wait mode, reduce power cons umption by disabling the hrp before executing the wait instruction. 10.6.2 stop mode the hrp is inactive after the execution of a stop instruction. the top and bot outputs are both set to logic 0 after execution of the stop instruction. entering stop mode causes the hrpen bit in the hrpctrl register to be set to 0. when the mcu exits stop mode after an external interrupt, the hrp resumes operation. note the hrp shutdown pin remains active during stop mode. 10.7 hrp during break interrupts the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see 19.2.2.5 break flag control register. to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bc fe is at 0. after the break, doing the second step clears the status bit. 10.7.1 input/output signals port b shares two of its pins with the hrp. the two output pins are ptb0/top and ptb1/bot. port c shares one of its pins (ptc2/shtdwn/irq) with the hrp. hrp registers mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 103 10.8 hrp registers the following registers control and monitor operation of the hrp: hrp control register (hrpctrl) hrp duty cycle registers (hrpdch: hrpdcl) hrp period registers (hrpperh:hrpperl) hrp deadtime register (hrpdt) hrp timebase registers (hrptbh:hrptbl) 10.8.1 hrp control register the hrpctrl register does the following: enables the hrp controls the operating mode of the hrp enables the shtdwn, top, and bot pins enables interrupt functionality for the shtdwn pin shtlvl ? shtdwn pin level this read-only bit contains the current logic level of the shtdwn pin. reset clears the shtlvl bit. hrpoe ? hrp output enable this read/write bit enables/disables the top and bot output pins. 1 = pins ptb0/top and ptb1/bot function as top and bot outputs from the hrp module. the contents of the port b data and data direction registers do not affect these pins. 0 = pins ptb0/top and ptb1/bot function as ptb0 and ptb1 general-purpose i/o pins. the state of these pins is controlled by the port b data and data direction registers. shtif ? shtdwn interrupt flag this read/write bit is set when a falling edge or a low level is detected on the shtdwn pin. reset clears the shtif bit. writing 0 to shtif clears the bit. 1 = shtdwn pin interrupt pending 0 = no shtdwn pin interrupt pending shtie ? shtdwn interrupt enable this read/write bit enables hrp cpu interrupt serv ice requests for the shtdwn pin. reset clears the shtie bit. 1 = shtdwn cpu interrupt requests enabled 0 = shtdwn cpu interrupt requests disabled shten ? shutdown pin enable address: $0051 bit 7654321bit 0 read: shtlvl hrpoe shtif shtie shten hrp- mode hrpen write: reset: 0000000 = unimplemented figure 10-10. hrp control register (hrpctrl) high resolution pwm (hrp) mc68hc908lb8 data sheet, rev. 0 104 freescale semiconductor this read/write bit enables the shtdwn func tionality on pin ptc2/shtdwn/irq. when shtdwn functionality is enabled, a falling edge or a low le vel on the shtdwn pin causes the top and bot outputs to be switched to logic 0 and the hrpen bit is set to logic 0, disabling the hrp. 1 = pin ptc2/shtdwn/irq functions as shtdwn input. 0 = pin ptc2/shtdwn/irq functions controlled by port c register note the top and bot pins must be enabled using the hrpoe bit for the hrpen bit to have any effect on th e ptb0/top and ptb1/bot i/o pins. hrpmode ? mode select this read/write bit selects between variable frequency and variable duty cycle modes of operation. 1 = variable duty cycle mode 0 = variable frequency mode hrpen ? enable this read/write bit enables/disables the hrp. 1 = hrp enabled 0 = hrp disabled when the hrp is disabled the top and bot outputs both sw itch to logic 0. if a logic 0 is detected on the shtdwn input pin, the module outputs both switch to logic 0 and the hrpen bit is automatically set to 0 to disable the module. note the top and bot pins must be enabled using the hrpoe bit for the hrpen bit to have any effect on th e ptb0/top and ptb1/bot i/o pins. 10.8.2 hrp duty cycle registers the two read/write duty cycle register s contain the 16-bit duty cycle of the output after dithering. it is split into two parts: 1. 11-bit duty cycle value (dc[10:0]) used to generate the hrp output waveforms. 2. 5-bit step value (step[4:0]) that defines the percentage of time spent on the larger of two duty cycle values in variable duty cycle mode. the duty cycle including dithering in variable duty cycle mode is: (eq 10-11) where 2 sel[2:0] is the step[4:0] scaling factor. hrpdch:hrpdcl are not used in variable frequency mode. the contents of the registers have no effect in this mode writes to the high byte (hrpdch) are stored in a la tch until the low byte (hrpdcl) is written. both registers are then updated simultaneously. this prevents glitches in the output duty cycle. output duty cycle dc 10:0 [] [] ?? ?? hrp registers mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 105 dc[10:0] ? 11-bit duty cycle value step[4:0] ? 5-bit dithering step value 10.8.3 hrp period registers the two read/write period registers contain the 16-bit per iod of the pwm output after dithering. it is split into two parts: 1. 11-bit period value (p[10:0]) used to generate the hrp?s output waveforms. 2. 5-bit step value (step[4:0]) the lower five bits of hrpperh:hrpperl, specifies how much time is spent on the longer period (period2). the output period including dithering in variable frequency mode is: (eq 10-12) where 2 sel[2:0] is the step[4:0] scaling factor. the output period in variable duty cycle mode does not include dithering. the period value is: (eq 10-13) writes to the high byte (hrpperh) are stored in a la tch until the low byte (hrpperl) is written. both registers are then updated simultaneously. this prevents glitches in the output period. address: hrpdch ? $0052 hrpdcl ? $0053 bit 15 14 13 12 11 10 9 bit 8 read: dc10 dc9 dc8 dc7 dc6 dc5 dc4 dc3 write: reset: 0 0000000 bit 7654321bit 0 read: dc2 dc1 dc0 step4 step3 step2 step1 step0 write: reset: 0 0000000 figure 10-11. hrp duty cycle registers (hrpdch:hrpdcl) address: hrpperh ? $0054 hrpperl ? $0055 bit 15 14 13 12 11 10 9 bit 8 read: p10p9p8p7p6p5p4p3 write: reset: 0 0000000 bit 7654321bit 0 figure 10-12. hrp period registers (hrpperh:hrpperl) output period (seconds) p10:0 [] [] ?? ?? high resolution pwm (hrp) mc68hc908lb8 data sheet, rev. 0 106 freescale semiconductor p[10:0] ? 11-bit period value step[4:0] ? 5-bit dithering step value 10.8.4 hrp deadtime register this read/write register contains an 8-bit value corre sponding to the number of hrpclk cycles that will be subtracted from the logic 1 level of the top and bot output signals to provide deadtime between the two signals. (eq 10-14) 10.8.5 frequency dithering hrp timebase registers the two read/write frequency dithering timebase re gisters hrptbh:hrptbl contain a 16-bit value used to determine the time base for switching between the two dithering frequencies. the timebase is calculated from the following formula: (eq 10-15) writes to the high byte (hrptbh) are stored in a latch until the low byte (hrptbl) is written. both registers are then updated simultaneously. this prevents glitches occurring on the output signal. read: p2 p1 p0 step4 step3 step2 step1 step0 write: reset: 0 0000000 address: $0056 bit 7654321bit 0 read: dt7 dt6 dt5 dt4 dt3 dt2 dt1 dt0 write: reset: 0 0001000 figure 10-13. hrp deadtime register (hrpdt) address: hrptbh ? $0057 hrptbl ? $0058 bit 15 14 13 12 11 10 9 bit 8 read: tb15 tb14 tb13 tb12 tb11 tb10 tb9 tb8 write: reset: 0 0000000 bit 7654321bit 0 read: tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 write: reset: 0 0000000 figure 10-14. hrp timebase registers (hrptbh:hrptbl) figure 10-12. hrp period registers (hrpperh:hrpperl) dead time hrpdt hrpclk ------------------------- - = frequency dithering timebase (seconds) hrptbh:hrptbl hrpclk ------------------------------------------------- - = hrp registers mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 107 10.8.6 frequency ditheri ng control register this read/write register selects the clock source for the dithering controller, and selects the number of dithering steps and modulus value of the dithering counter. clksrc ? dithering clock source this read/write bit selects the clock source for the 5-bit dithering counter. 1 = the dithering counter is cl ocked from the 16-bit timebase 0 = the dithering counter is clocked from the output of the dual frequency generator counter sel[2:0] ? dithering step/modulus select these read/write bits select the number of steps used by the dithering counter and set the scaling factor for the step[4:0] bits. address: $0059 bit 15 14 13 12 11 10 9 bit 8 read: clksrc sel2 sel1 sel0 write: reset: 0000 = unimplemented figure 10-15. frequency dither ing control register (hrpdcr) table 10-5 clksel clock source timebase 0 dual frequency generator 1 16 bit timebase table 10-6 sel[2:0] number of steps divide step[4:0] by... 0 32 1 1 16 2 2 8 4 3 4 8 4 2 16 5 (1) notes: 1. no dithering occurs for this setting. 0 32 6 reserved reserved 7 reserved reserved p(10:0) hrpclk ------------------------- - hrptbh:hrptbl hrpclk ------------------------------------------------- - high resolution pwm (hrp) mc68hc908lb8 data sheet, rev. 0 108 freescale semiconductor 10.9 hrp programming examples the hrp has been designed to simplify the software r equired to generate typical control waveforms and reduce the cpu load. the following examples show how to calculate the register values needed to generate the desired output frequencies, resolutions, deadtime, etc. the exampl es consider only the case of variable frequency mode, but the calculations for variable duty cycle mode are very similar. example 1 this example shows how to configure the module to output a frequency of 132.073 khz, with an hrpclk of 8 mhz. (eq 10-16) (eq 10-17) and (eq 10-18) if we use 32 steps, simplifying the last equation gives (eq 10-19) therefore, (eq 10-20) if we choose step[4:0] = 19, the output frequency = 132.026 khz. if we choose step[4:0] = 18, the output frequency = 132.094 khz. so step[4:0] = 19 gets us closer to our desired frequency of 132.073 khz in this case, the switching frequency is 132.094 khz/32 = 4.1279 khz. period (seconds) 10 3 ? 132.073 --------------------- 7 . 5 7 1 5 7 1 0 6 ? p10:0 [] [] ?? ?? [] [] ?? ?? [] [] ?? ?? [] [] hrp programming examples mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 109 example 2 this example shows how to configure the module to output a frequency of 81.5 khz, with a deadtime of 10 s. the system has an hrpclk of 8 mhz, and the switching frequency must be less than 100 hz. (eq 10-21) (eq 10-22) and (eq 10-23) if we use 32 steps, simplifying the last equation gives (eq 10-24) (eq 10-25) if we choose step[4:0] = 5, the output frequency = 81.5027 khz. in this case (using the output of the dual freq uency generator as source for the dithering timebase), (eq 10-26) to achieve a switching frequency of less than 100 hz , we must use the 16-bit timebase counter as the source for the dithering timebase. (eq 10-27) (eq 10-28) to insert a 10 s deadtime in the output signals, we must calculate the value to store in the hrpdt register from the following equation. (eq 10-29) (eq 10-30) i.e. (eq 10-31) period (seconds) 10 3 ? 81.5 ----------- 1 2 . 2 6 9 9 1 0 6 ? p 10:0 [] [] ?? ?? [] [] ?? ?? [] [] ?? ?? [] [] ? hrpdt 810 6 -------------------- = hrpdt 10 8 80$50 === high resolution pwm (hrp) mc68hc908lb8 data sheet, rev. 0 110 freescale semiconductor mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 111 chapter 11 low-power modes 11.1 introduction the microcontroller (mcu) may enter two low-pow er modes: wait mode and stop mode. they are common to all hc08 mcus and are entered through in struction execution. this section describes how each module acts in the low-power modes. 11.1.1 wait mode the wait instruction puts the mcu in a low-power standby mode in which the central processor unit (cpu) clock is disabled but the bus clock continues to run. power consumption can be further reduced by disabling the low-voltage inhibit (lvi) module through bits in the config1 register. see chapter 5 configuration register (config) . 11.1.2 stop mode stop mode is entered when a stop instruction is ex ecuted. the cpu clock is disabled and the bus clock is disabled. 11.2 analog-to-digi tal converter (adc) 11.2.1 wait mode the analog-to-digital converter (adc) continues normal operation during wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting adch4?adch0 bits in the adc status and control register before executing the wait instruction. 11.2.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode after an external interrupt. allow one conversion cycle to stabi lize the analog circuitry. 11.3 break module (brk) 11.3.1 wait mode if enabled, the break (brk) module is ac tive in wait mode. in the break routine, the user can subtract one from the return address on the stack if the sbsw bit in the break status register is set. low-power modes mc68hc908lb8 data sheet, rev. 0 112 freescale semiconductor 11.3.2 stop mode the break module is inactive in stop mode. the stop instruction does not affect break module register states. 11.4 central pro cessor unit (cpu) 11.4.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains cl ear. after exit by reset, the i bit is set. disables the cpu clock 11.4.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the conditi on code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins ru nning after the oscillator stabilization delay. 11.5 computer operatin g properly module (cop) 11.5.1 wait mode the cop remains active during wait mode. if cop is enabled, a reset will occur at cop timeout. 11.5.2 stop mode stop mode turns off the copclk input to the cop and clears the cop prescaler. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. the stop bit in the config1 register enables the stop instruction. to prevent inadvertently turning off the cop with a stop instruction, disable the stop instruction by clearing the stop bit. 11.6 external inte rrupt module (irq) 11.6.1 wait mode the external interrupt (irq ) module remains active in wait mode. clearing the imask bit in the irq status and control register enables irq cpu interrupt requests to bring the mcu out of wait mode if irq function is enabled. 11.6.2 stop mode the irq module remains active in stop mode. clearing the imask bit in the irq status and control register enables irq cpu interrupt requests to bring the mcu out of stop mode. keyboard interrup t module (kbi) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 113 11.7 keyboard inte rrupt module (kbi) 11.7.1 wait mode the keyboard interrupt (kbi) modul e remains active in wait mode . clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. 11.7.2 stop mode the keyboard module remain s active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. 11.8 high resolution pwm (hrp) 11.8.1 wait mode the hrp remains active after the execution of a wait instruction. in wait mode the hrp registers are not accessible by the cpu. any enabled cpu interrupt request from the hrp can bring the mcu out of wait mode. if hrp functions are not required during wait mode, reduce power consumption by stopping the hrp before executing the wait instruction. 11.8.2 stop mode the hrp is inactive after the execution of a stop instruction. the top and bot outputs are both set to logic 0 and the hrpen bit in the hrpctrl register is set to 0 after execution of the stop instruction. the stop instruction does not affect other register conditions or the state of the hrp counters. when the mcu exits stop mode after an external interrupt, th e hrp is inactive because the hrpen bit is set to 0. note the hrp shutdown pin remains active during stop mode. 11.9 low-voltage inhibit module (lvi) 11.9.1 wait mode if enabled, the low-voltage inhibit (lvi) module remains active in wait mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. 11.9.2 stop mode if enabled, the lvi module remains active in st op mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of stop mode. low-power modes mc68hc908lb8 data sheet, rev. 0 114 freescale semiconductor 11.10 op amp/comparator 11.10.1 wait mode while in wait the state of the op amp/comparator cannot be changed. if the op amp/comparator module is not needed during wait mode, reduce power consumpt ion by disabling the op amp/comparator before executing the wait command. 11.10.2 stop mode the op amp/comparator is inactive after executio n of the stop command. the op amp/comparator will be in a low-power state and will not drive its output pin. when the mcu exits stop mode after and external interrupt, the op amp/comparator continues operation. 11.11 oscillator module (osc) 11.11.1 wait mode the wait instruction has no effect on the oscillator logic. busclkx2 and busclkx4 continue to drive to the sim module. 11.11.2 stop mode the stop instruction disables either the xtalclk, the rcclk, or intclk output, hence busclkx2 and busclkx4. 11.12 pulse-width mo dulator module (pwm) 11.12.1 wait mode when the microcontroller is put in low-power wait mode via the wait instruction, all clocks to the pwm module will continue to run. if an interrupt is issued from the pwm module (via a reload or a fault), the microcontroller will exit wait mode. clearing the pwmen bit before entering wait mode wi ll reduce power consumption in wait mode because the counter, prescaler divider, and ldfq divider wi ll no longer be clocked. in addition, power will be reduced because the pwms will no longer toggle. 11.12.2 stop mode when the microcontroller is put into stop mode via t he stop instruction, the pwm will stop functioning. the pwm0 and pwm1 outputs are set to logic 0. the stop instruction does not affect the register conditions or the state of the pwm counters. when th e mcu exits stop mode after an external interrupt the pwm resumes operation. timer interface module (tim) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 115 11.13 timer interface module (tim) 11.13.1 wait mode the timer interface module (tim) remains active in wait mode. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, r educe power consumption by stopping the tim before executing the wait instruction. 11.13.2 stop mode the tim is inactive in stop mode. the stop instruction does not affect register states or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. 11.14 exiting wait mode these events restart the cpu clock and load the program counter with the reset vector or with an interrupt vector: external reset ? a logic 0 on the rst pin resets the mcu and loads the program counter with the contents of locations: $ffff and $fffe. external interrupt ? a high-to-low trans ition on an external interrupt pin (irq pin) loads the program counter with the contents of locations: $fffb and $fffa. break (brk) interrupt ? a break interrupt loads the program counter with the contents of: $fffd and $fffc. computer operating properly (cop) module reset ? a timeout of the cop counter resets the mcu and loads the program counter with the contents of: $ffff and $fffe. low-voltage inhibit (lvi) module reset ? a power supply voltage below the v tripf voltage resets the mcu and loads the program counter with the contents of locations: $ffff and $fffe. keyboard interrupt (kbi) module ? a cpu inte rrupt request from the kbi module loads the program counter with the contents of: $ffe1 and $ffe0. timer interface (tim) module interrupt ? a cpu interrupt request from the tim loads the program counter with the contents of: ? $fff3 and $fff2; tim overflow ? $fff5 and $fff4; tim channel 1 ? $fff7 and $fff6; tim channel 0 analog-to-digital converter (adc) module interrupt ? a cpu interrupt request from the adc loads the program counter with the contents of: $ffdf and $ffde. pulse-width modulator with fault input (pwm) ? a cpu interrupt request from the pwm load the program counter with the contents of: ? $fff1 and $fff0; fault ? $ffef and $ffee; pwmint high resolution pwm (hrp) ? a cpu interrupt request from the hrp loads the program counter with the contents of: $ffed and $ffec low-power modes mc68hc908lb8 data sheet, rev. 0 116 freescale semiconductor 11.15 exiting stop mode these events restart the system clocks and load the program counter with the reset vector or with an interrupt vector: external reset ? a logic 0 on the rst pin resets the mcu and loads the program counter with the contents of locations $ffff and $fffe. external interrupt ? a high-to-low transition on an external interrupt pin loads the program counter with the contents of locations: ? $fffb and $fffa; irq pin ? $ffe1 and $ffe0; keyboard interrupt pins low-voltage inhibit (lvi) reset ? a power supply voltage below the lvi tripf voltage resets the mcu and loads the program counter with the contents of locations $ffff and $fffe. break (brk) interrupt ? a break interrupt loads the program counter with the contents of locations $fffd and $fffc. keyboard (kbi) interrupt ? a keyboard interrupt loads the program counter with contents of location $ffe1 and $ffe0 . upon exit from stop mode, the system clocks begin running after an o scillator stabilization delay. a 12-bit stop recovery counter inhibits the system clocks fo r 4096 busclkx4 cycles after the reset or external interrupt. the short stop recovery bit, ssrec, in the config1 register controls the oscillator stabilization delay during stop recovery. setting ssrec reduces stop recovery time from 4096 busclkx4 cycles to 32 busclkx4 cycles. note use the full stop recovery time (ssrec = 0) in applications that use an external crystal. mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 117 chapter 12 low-voltage inhibit (lvi) 12.1 introduction this section describes the low-voltage inhibit (lvi) module, which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls below the lvi trip falling voltage, v tripf . 12.2 features features of the lvi module include: programmable lvi reset programmable power consumption selectable lvi trip voltage programmable stop mode operation 12.3 functional description figure 12-1 shows the structure of the lvi module. lvistop, lvipwrd, and lvirstd are user selectable options found in the conf iguration register (config1). see chapter 5 configuration register (config) . figure 12-1. lvi module block diagram low v dd detector lvipwrd stop instruction lvistop lvi reset lviout v dd > lvitrip = 0 v dd lvitrip = 1 from config from config v dd from config lvirstd low-voltage inhibit (lvi) mc68hc908lb8 data sheet, rev. 0 118 freescale semiconductor the lvi is enabled out of reset. the lvi module c ontains a bandgap reference circuit and comparator. clearing the lvi power disable bit, lvip wrd, enables the lvi to monitor v dd voltage. clearing the lvi reset disable bit, lvirstd, enables the lvi module to generate a reset when v dd falls below a voltage, v tripf . setting the lvi enable in stop mode bit, lvis top, enables the lvi to operate in stop mode. once an lvi reset o ccurs, the mcu remains in reset until v dd rises above a voltage, v tripr , which causes the mcu to exit reset. see chapter 17 system integration module (sim) for the reset recovery sequence. the output of the comparator controls the state of the lviout flag in the lvi status register (lvisr) and can be used for polling lvi operat ion when the lvi reset is disabled. 12.3.1 polled lvi operation in applications that can operate at v dd levels below the v tripf level, software can monitor v dd by polling the lviout bit. in the configuration register, the lvip wrd bit must be at 0 to enable the lvi module, and the lvirstd bit must be at 1 to disable lvi resets. 12.3.2 forced reset operation in applications that require v dd to remain above the v tripf level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls below the v tripf level. in the configuration register, the lvipwrd and lvirstd bits must be at 0 to enable the lvi module and to enable lvi resets. 12.3.3 voltage hyst eresis protection once the lvi has triggered (by having v dd fall below v tripf ), the lvi will maintain a reset condition until v dd rises above the rising trip point voltage, v tripr . this prevents a condition in which the mcu is continually entering and exiting reset if v dd is approximately equal to v tripf . v tripr is greater than v tripf by the hysteresis voltage, v hys . lvi status register mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 119 12.4 lvi status register the lvi status register (lvisr) indicates if the v dd voltage was detected below the v tripf level while lvi resets have been disabled. lviout ? lvi output bit this read-only flag becomes set when the v dd voltage falls below the v tripf trip voltage and is cleared when v dd voltage rises above v tripr . the difference in these threshold levels results in a hysteresis that prevents oscillation into and out of reset (see table 12-1 ). reset clears the lviout bit. 12.5 lvi interrupts the lvi module does not generate interrupt requests. 12.6 low-power modes the stop and wait instructions put the mcu in low power- consumption standby modes. 12.6.1 wait mode if enabled, the lvi module remains active in wait m ode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. 12.6.2 stop mode when the lvipwrd bit in the configuration register is cleared and the lvistop bit in the configuration register is set, the lvi module remains active in st op mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of stop mode. address: $fe0c bit 7654321bit 0 read:lviout000000r write: reset:00000000 = unimplemented r = reserved figure 12-2. lvi status register (lvisr) table 12-1. lviout bit indication v dd lviout v dd > v tripr 0 v dd < < < low-voltage inhibit (lvi) mc68hc908lb8 data sheet, rev. 0 120 freescale semiconductor mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 121 chapter 13 oscillator module (osc) 13.1 introduction the oscillator module is used to provide a stable clock source for t he microcontroller system and bus. the oscillator module generates two output clocks, bu sclkx2 and busclkx4. the busclkx4 clock is used by the system integration module (sim) and the computer operating properly module (cop). the busclkx2 clock is divided by two in the sim to be used as the bus clock for the microcontroller. therefore the bus frequency will be one forth of the busclkx4 frequency. 13.2 features the oscillator has these four clock source options available: 1. internal oscillator: an internally gener ated, fixed frequency clock, trimmable to 5% oscillator module (osc) mc68hc908lb8 data sheet, rev. 0 122 freescale semiconductor figure 13-1. block diagram highlighting osc block and pins 13.3.1 internal oscillator the internal oscillator circuit is designed for use wi th no external components to provide a clock source with tolerance less than 25% untrimmed. an 8-bit trimming register allows the adjust to a tolerance of less than 5%. the internal oscillator will generate a clock of 16 mhz typical (intclk) resulting in a bus speed (internal clock m68hc08 cpu control and status user flash ? 8 kbytes user ram ? 128 bytes monitor rom ? 350 bytes user flash vector space ? 34 bytes ddrb portb ddrc portc internal bus pta6 (1) /ad5/tch0/kbi6 pta5 (1) /rst /kbi5 pta4 (1) /ad4/kbi4 pta3 (1) /ad3/kbi3 pta2 (1) /ad2/kbi2 pta1 (1) /ad1/kbi1 pta0 (1) /ad0/kbi0 ptb7/v out /ad6/fault (2) ptb6/v? ptb5/v+ ptb4/pwm1 ptb3/pwm0 ptb2/fault (2) ptb1/bot ptb0/top ptc1 (1) /osc2 ptc0 (1) /osc1 power v ss v dd ddra porta ptc2 (1) /shtdwn/irq flash programming oscillator cpu registers arithmetic/logic unit (alu) system integration module dual channel pwm module high resolution pwm module low-voltage inhibit module computer operating properly module 2-channel timer module 8-bit analog-to-digital converter module op amp/comparator module keyboard interrupt module module routines rom ? 674 bytes registers ? 64 bytes 1. pin contains integrated pullup device. 2. fault function switchable between pins ptb2 and ptb7. notes: functional description mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 123 13.3.1.1 internal oscillator trimming the 8-bit trimming register, osctrim, allows a clock period adjust of +127 and ?128 steps. increasing osctrim value increases the clock per iod. trimming will allow the inte rnal clock frequency value fit in a 5% range around 16 mhz. the oscillator will be trimmed at the factory. t he trimming value will be pr ovided in a known flash location, $ffc0. so that the user would be able to copy this byte from the flash to the osctrim register right at the beginning of assembly code. reset loads osctrim with a default value of $80. 13.3.1.2 internal to external clock switching when external clock source (external osc, rc, or xtal) is desired, the user must perform the following steps: 1. for external crystal circuits only, oscopt[1:0] = 1:1: to hel p precharge an external crystal oscillator, set ptc1 (osc2) as an output and dr ive high for several cycles. this may help the crystal circuit start more robustly. 2. set config2 bits oscopt[1:0] according to table 13-2 . the oscillator modul e control logic will then set osc1 as an external clock input and, if th e external crystal option is selected, osc2 will also be set as the clock output. 3. create a software delay to wait the stabilization time needed for the selected clock source (crystal, resonator, rc) as recommended by the component manufacturer. a good rule of thumb for crystal oscillators is to wait 4096 cycles of the cr ystal frequency, i.e., for a 4-mhz crystal, wait approximately 1 ms. 4. after the manufacturer?s recommended delay has elapsed, the ecgon bit in the osc status register (oscstat) needs to be set by the user software. 5. after ecgon set is detected, the osc module checks for oscillator activity by waiting two external clock rising edges. 6. the osc module then switches to the external clock. logic provides a glitch free transition. 7. the osc module first sets the ecgst bit in the oscstat register and then stops the internal oscillator. note once transition to the external clock is done, the internal oscillator will only be reactivated with reset. no post-switch clock monitor feature is implemented (clock does not switch back to internal if external clock dies). 13.3.2 external oscillator the external clock option is designed for use when a cl ock signal is avai lable in the application to provide a clock source to the microcontroller. the osc1 pin is enabled as an input by the oscillator module. the clock signal is used directly to create busclkx4 and also divided by two to create busclkx2. in this configuration, the osc2 pin cannot output busclkx4. so the osc2en bit in the port c pullup enable register will be clear to enable ptc1 i/o functions on the pin. oscillator module (osc) mc68hc908lb8 data sheet, rev. 0 124 freescale semiconductor 13.3.3 xtal oscillator the xtal oscillator circuit is designed for use with an external crystal or cera mic resonator to provide an accurate clock source. in this configuration, the osc2 pin is dedicated to the external crystal circuit. the osc2en bit in the port c pullup enable register ha s no effect when this clock mode is selected. in its typical configuration, the xtal oscillator is conn ected in a pierce oscillator configuration, as shown in figure 13-2 . this figure shows only the logical repres entation of the internal components and may not represent actual circuitry. the oscillat or configuration us es five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) note the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be r equired for all ranges of operation, especially with high frequency crystals. refer to the crystal manufacturer?s data for more information. 13.3.4 rc oscillator the rc oscillator circuit is designed for use with extern al r to provide a clock source with tolerance less than 25%. see figure 13-3 . in its typical configuration, the rc oscillator requires two external components, one r and one c. in the mc68hc908lb8, the capacitor is internal to the chip. the r value should have a tolerance of 1% or less, to obtain a clock source with less than 25% toler ance. the oscillator configuration uses one component, r ext . in this configuration, the osc2 pin can be left in the reset state as ptc1. or, the osc2en bit in the port c pullup enable register can be set to enable the osc2 function on the pin without affecting the clocks. functional description mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 125 figure 13-2. xtal oscillator external connections figure 13-3. rc oscillator external connections c 1 c 2 simoscen xtalclk r b x 1 r s (1) mcu from sim osc2 osc1 2 busclkx2 busclkx4 to sim to sim note 1: r s can be zero (shorted) when used with higher frequency crystals. refer to manufacturer?s data. see chapter 20 electrical specifications for component value requirements. mcu r ext simoscen osc1 external rc oscillator en rcclk 2 busclkx2 busclkx4 to sim from sim v dd ptc1 i/o 1 0 ptc1 osc2en ptc1/busclkx4 (osc2) to sim see chapter 20 electrical specifications for component value requirements. 0 1 intclk oscrcopt oscillator module (osc) mc68hc908lb8 data sheet, rev. 0 126 freescale semiconductor 13.4 oscillator module signals the following paragraphs describe the signals that ar e inputs to and outputs from the oscillator module. 13.4.1 crystal amplif ier input pin (osc1) the osc1 pin is either an input to the crystal oscillat or amplifier, an input to the rc oscillator circuit, or an external clock source. for the internal oscillator configuration, the os c1 pin can assume other functions according to table 13-1 . 13.4.2 crystal amplifier out put pin (osc2/ptc1/busclkx4) for the xtal oscillator device , the osc2 pin is the crystal osc illator inverting amplifier output. for the external clock option, the osc2 pin is dedi cated to the ptc1 i/o function. the osc2en bit has no effect. for the internal oscillator or rc oscillator options, th e osc2 pin can assume other functions according to table 13-1 , or the output of the oscillator clock (busclkx4). 13.4.3 oscillator e nable signal (simoscen) the simoscen signal comes from the system integration module (sim) and enables/disables either the xtal oscillator circuit, th e rc oscillator, or the internal oscillator. 13.4.4 xtal oscill ator clock (xtalclk) xtalclk is the xtal oscillator output signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 13-2 shows only the logical relation of xtalclk to osc1 and osc2 and may not represent the actual circui try. the duty cycle of xtalclk is unknown and may depend on the crystal and other external factors. al so, the frequency and amplitude of xtalclk can be unstable at start up. 13.4.5 rc oscillat or clock (rcclk) rcclk is the rc oscillator output signal. its frequency is directly proportional to the time constant of external r and internal c. figure 13-3 shows only the logical relation of rcclk to osc1 and may not represent the actual circuitry. table 13-1. osc2 pin function option osc2 pin function xtal oscillator inverting osc1 external clock ptc1 i/o internal oscillator or rc oscillator controlled by osc2en bit in ptcpue register osc2en = 0: ptc1 i/o osc2en = 1: busclkx4 output low power modes mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 127 13.4.6 internal osci llator clock (intclk) intclk is the internal oscillator output signal. its nomin al frequency is fixed to 16 mhz, but it can be also trimmed using the oscillato r trimming feature of the osctrim register (see 13.3.1.1 internal oscillator trimming). 13.4.7 oscillator out 2 (busclkx4) busclkx4 is the same as the input clock (xtalclk , rcclk, or intclk). this signal is driven to the sim module and is used to determine the cop cycles. 13.4.8 oscillator out (busclkx2) the frequency of this signal is equal to half of the busclkx4, this signal is driven to the sim for generation of the bus clocks used by the cpu and other modules on the mcu. busclkx2 will be divided again in the sim and results in the internal bus frequency being one fourth of either the xtalclk, rcclk, or intclk frequency. 13.5 low power modes the wait and stop instructions put the mcu in low-power consumption standby modes. 13.5.1 wait mode the wait instruction has no effect on the oscillator logic. busclkx2 and busclkx4 continue to drive to the sim module. 13.5.2 stop mode the stop instruction disables either the xtalclk, the rcclk, or intclk output, hence busclkx2 and busclkx4. 13.6 oscillator during break mode the oscillator continues to drive busclkx2 and busclkx4 when the device enters the break state. 13.7 config2 options two config2 register options affect the operation of the oscillator module: oscopt1 and oscopt0. all config2 register bits will hav e a default configuration. refer to chapter 5 configuration register (config) for more information on how the config2 register is used. table 13-2 shows how the oscopt bits are used to select the oscillator clock source. oscillator module (osc) mc68hc908lb8 data sheet, rev. 0 128 freescale semiconductor 13.8 input/output (i/o) registers the oscillator module contains these two registers: 1. oscillator status register (oscstat) 2. oscillator trim register (osctrim) 13.8.1 oscillator status register the oscillator status register (oscstat) contains the bits for switching from internal to external clock sources. ecgon ? external clock generator on bit this read/write bit enables external clock generator, so that the switching process can be initiated. this bit is forced low during reset. this bit is ignored in monitor mode when the internal oscillator is bypassed. 1 = external clock generator enabled 0 = external clock generator disabled table 13-2. oscillator modes oscopt1 oscopt0 oscillator modes 0 0 internal oscillator 0 1 external oscillator 10 external rc 1 1 external crystal address: $0036 bit 7654321bit 0 read: rrrrrrecgon ecgst write: reset:00000000 r = reserved figure 13-4. oscillator status register (oscstat) input/output (i/o) registers mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 129 ecgst ? external clock status bit this read-only bit indicates whether or not an exte rnal clock source is engaged to drive the system clock. 1 = an external clock source engaged 0 = an external clock source disengaged 13.8.2 oscillator tr im register (osctrim) trim7?trim0 ? internal oscillator trim factor bits these read/write bits change the size of the intern al capacitor used by the internal oscillator. by measuring the period of the internal clock and adjusti ng this factor accordingly, the frequency of the internal clock can be fine tuned. increasing (decreas ing) this factor by one increases (decreases) the period by appoximately 0.2% of the untrimmed period (the period for trim = $80). the trimmed frequency is guaranteed not to vary by more than 5 % over the full specifi ed range of temperature and voltage. the reset value is $80, which sets the frequency to 16 mhz (4.0 mhz bus speed) 25%. address: $0038 bit 7654321bit 0 read: trim7 trim6 trim5 trim4 trim3 trim2 trim1 trim0 write: reset:10000000 figure 13-5. oscillator trim register (osctrim) oscillator module (osc) mc68hc908lb8 data sheet, rev. 0 130 freescale semiconductor mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 131 chapter 14 input/output (i/o) ports 14.1 introduction bidirectional input-output (i/o) pins form three paralle l ports. all i/o pins are programmable as inputs or outputs. all individual bits within port a and port c are software configurable with pullup devices if configured as input port bits. the pullup devices ar e automatically and dynamically disabled when a port bit is switched to output mode. note connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. addr.register name bit 7654321bit 0 $0000 port a data register (pta) see page 132. read: 0 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) see page 134. read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) see page 136. read:00000ptc2 ptc1 ptc0 write: reset:00000000 $0004 data direction register a (ddra) see page 133. read: 0 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) see page 135. read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) see page 137. read:000000 ddrc1 ddrc0 write: reset:00000000 = unimplemented figure 14-1. i/o port register summary input/output (i/o) ports mc68hc908lb8 data sheet, rev. 0 132 freescale semiconductor 14.2 port a port a is an 7-bit special-function port that shares all of its pins with the keyboard interrupt (kbi) module, the analog-to-digital converter (adc) module, the reset pin, and timer channel 0. see table 1-1 . pin functions for a description of the priority of these functi ons. port a also has software configurable pullup devices if configured as an input port. 14.2.1 port a data register the port a data register (pta) contains a data latch for each of the seven port a pins. pta6?pta0 ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction regi ster a. reset has no effect on port a data. kbd6?kbd0 ? keyboard inputs the keyboard interrupt enable bits, kbie6?kbie0, in the keyboard interrupt control register (kbicr) enable the port a pins as external interrupt pins. see chapter 9 keyboard interrupt module (kbi). 14.2.2 data dir ection register a data direction register a (ddra) determines whether each port a pin is an input or an output. writing a 1 to a ddra bit enables the output buffer for the corresponding port a pin; a 0 disables the output buffer. $000d port a input pullup enable register (ptapue) see page 134. read: pta6pue pta5pue pta4pue pta3pue pta2pue pta1pue pta0pue write: reset:-0000000 $000e port c input pullup enable register (ptcpue) see page 138. read: osc2en 0000 ptcpue2 ptcpue1 ptcpue0 write: reset:00000000 address: $0000 bit 7654321bit 0 read: pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset = unimplemented figure 14-2. port a data register (pta) addr.register name bit 7654321bit 0 = unimplemented figure 14-1. i/o port register summary (continued) port a mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 133 ddra6?ddra0 ? data direction register a bits these read/write bits control port a data directio n. reset clears ddra6?ddra0, configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note avoid glitches on port a pins by writin g to the port a data register before changing data direction regist er a bits from 0 to 1. figure 14-4 shows the port a i/o logic. figure 14-4. port a i/o circuit when bit ddrax is a 1, reading address $0000 reads the ptax data latch. when bit ddrax is a 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 14-1 summarizes the operation of the port a pins. address: $0004 bit 7654321bit 0 read: 0 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 14-3. data direction register a (ddra) table 14-1. port a pin functions ptapue bit ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 10 x (1) input, v dd (2) ddra6?ddra0 pin pta6?pta0 (3) 00x input, hi-z (4) ddra6?ddra0 pin pta6?pta0 (3) x 1 x output ddra6?ddra0 pta6?pta0 pta6?pta0 read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus v dd ptapuex internal pullup device input/output (i/o) ports mc68hc908lb8 data sheet, rev. 0 134 freescale semiconductor 14.2.3 port a input pullup enable register the port a input pullup enable register (ptapue) cont ains a software configur able pullup device for each of the seven port a pins. each bit is individually conf igurable and requires that the data direction register, ddra, bit be configured as an input. ea ch pullup is automati cally and dynamically disabled when a port bit?s ddra is configured for output mode. pta6pue?pta0pue ? port a input pullup enable bits these writable bits are software programmable to enable pullup devices on an input port bit. 1 = corresponding port a pin configured to have internal pullup 0 = corresponding port a pin has internal pullup disconnected 14.3 port b port b is an 8-bit special-function port that shares a ll eight of its pins with the high resolution pwm (hrp), pulse-width modulator (pwm) module, and op amp/comparator module. see table 1-1 . pin functions for a description of the priority of these functions. 14.3.1 port b data register the port b data register (ptb) contains a data latch for each of the eight port pins. ptb7?ptb0 ? port b data bits these read/write bits are software-programmable. data direction of each port b pin is under the control of the corresponding bit in data direction regi ster b. reset has no effect on port b data. notes: 1. x = don?t care 2. i/o pin pulled up to v dd by internal pullup device 3. writing affects data register, but does not affect input. 4. hi-z = high impedance address: $000d bit 7654321bit 0 read: pta6pue pta5pue pta4pue pta3pue pta2pue pta1pue pta0pue write: reset:-0000000 figure 14-5. port a input pullup enable register (ptapue) address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset figure 14-6. port b data register (ptb) port b mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 135 14.3.2 data dir ection register b data direction register b (ddrb) determines whether each port b pin is an input or an output. writing a 1 to a ddrb bit enables the output buffer for the corresponding port b pin; a 0 disables the output buffer. ddrb7?ddrb0 ? data direction register b bits these read/write bits control port b data directio n. reset clears ddrb7?ddrb0, configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note avoid glitches on port b pins by writin g to the port b data register before changing data direction regist er b bits from 0 to 1. figure 14-8 shows the port b i/o logic. figure 14-8. port b i/o circuit when bit ddrbx is a 1, reading address $0001 reads the ptbx data latch. when bit ddrbx is a 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 14-2 summarizes the operation of the port b pins. address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 14-7. data direction register b (ddrb) read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus input/output (i/o) ports mc68hc908lb8 data sheet, rev. 0 136 freescale semiconductor 14.4 port c port c is a 3-bit, general-purpose bidirectional i/o por t. port c shares its pins with the oscillator (osc) module, high resolution pwm (hrp), and the external interrupt module (irq). see table 1-1 . pin functions for a description of the priority of these functi ons. port c also has software configurable pullup devices if configured as an input port. note ptc2 is input only. when the irq function is enabled in the configuration register 2 (config2), bit 2 of the port c data register (ptc) will always read 0. in this case, the bih and bil instructions can be used to read the logic level on the ptc2 pin. when the irq function is disabled, these instructions will behave as if the ptc2 pin is a logic 1. however, reading bit 2 of ptc will read the actual logic level on the pin. 14.4.1 port c data register the port c data register (ptc) contains a dat a latch for each of the seven port c pins. ptc2?ptc0 ? port c data bits these read/write bits are software-programmable. da ta direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. 14.4.2 data dir ection register c data direction register c (ddrc) determines whether ea ch port c pin is an input or an output. writing a 1 to a ddrc bit enables the output buffer for the corresponding port c pin; a 0 disables the output buffer. table 14-2. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0 x (1) notes: 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrb7?ddrb0 pin ptb7?ptb0 (3) 3. writing affects data register, but does not affect input. 1 x output ddrb7?ddrb0 ptb7?ptb0 ptb7?ptb0 address: $0002 bit 7654321bit 0 read:00000ptc2 ptc1 ptc0 write: reset:00000000 = unimplemented figure 14-9. port c data register (ptc) port c mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 137 ddrc1?ddrc0 ? data direction register c bits these read/write bits control po rt c data direction. reset clears ddrc1?ddrc0, configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note avoid glitches on port c pins by writin g to the port c data register before changing data direction regist er c bits from 0 to 1. figure 14-11 shows the port c i/o logic. figure 14-11. port c i/o circuit note figure 14-11 does not apply to ptc2. when bit ddrcx is a 1, reading address $0002 reads the ptcx data latch. when bit ddrcx is a 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 14-3 summarizes the operation of the port c pins. address: $0006 bit 7654321bit 0 read:000000 ddrc1 ddrc0 write: reset:00000000 = unimplemented figure 14-10. data direction register c (ddrc) read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus v dd internal ptcpuex pullup device input/output (i/o) ports mc68hc908lb8 data sheet, rev. 0 138 freescale semiconductor 14.4.3 port c input pullup enable register the port c input pullup enable register (ptcpue) co ntains a software configur able pullup device for each of the seven port c pins. each bit is individually c onfigurable and requires that the data direction register, ddrc, bit be configured as an input. each pullup is automatically and dynamically disabled when a port bit?s ddrc is configured for output mode. osc2en ? enable ptc1 on osc2 pin this read/write bit configures the osc2 pin function when internal oscillator or rc oscillator option is selected. this bit has no effect for the xtal or external oscillator options. 1 = osc2 pin outputs the internal or rc oscillator clock (busclkx4) 0 = osc2 pin configured for ptc1 i/o, ha ving all the interrupt and pullup functions ptcpue2?ptcpue0 ? port c input pullup enable bits these writable bits are software programmable to enable pullup devices on an input port bit. 1 = corresponding port c pin configured to have internal pullup 0 = corresponding port c pin internal pullup disconnected table 14-3. port c pin functions ptcpue bit ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write (1) notes: 1. output does not apply to ptc2. 10 x (2) 2. x = don?t care input, v dd (3) 3. i/o pin pulled up to v dd by internal pullup device. ddrc1?ddrc0 pin ptc1?ptc0 (4) 4. writing affects data register, but does not affect input. 00x input, hi-z (5) 5. hi-z = high impedance ddrc1?ddrc0 pin ptc1?ptc0 (4) x 1 x output ddrc1?ddrc0 ptc2?ptc0 ptc1?ptc0 address: $000e bit 7654321bit 0 read: osc2en 0000 ptcpue2 ptcpue1 ptcpue0 write: reset:00000000 = unimplemented figure 14-12. port c input pullup enable register (ptcpue) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 139 chapter 15 pulse width modulator with fault input (pwm) 15.1 introduction this section describes the pulse-width modulato r with fault input (pwm). the mc68hc908lb8 pwm module can generate two independent pwm signals. these pwm signals are edge-aligned. a block diagram of the pwm module is shown in figure 15-2 . a 12-bit timer pwm counter is common to both c hannels. pwm resolution is one clock period for edge-aligned operation. the clock period is dependent on the internal operating frequency (busclk) and a programmable prescaler. the highest resolution for edge-aligned operation is 125 ns (busclk = 8 mhz). a summary of the pwm registers is shown in figure 15-3 . 15.2 features features of the pwmmc include: two independent pwm signals edge-aligned pwm signals pwm signal polarity control programmable fault protection pulse width modulator with fault input (pwm) mc68hc908lb8 data sheet, rev. 0 140 freescale semiconductor figure 15-1. block diagramhighlighting pwm block and pins m68hc08 cpu control and status user flash ? 8 kbytes user ram ? 128 bytes monitor rom ? 350 bytes user flash vector space ? 34 bytes ddrb portb ddrc portc internal bus pta6 (1) /ad5/tch0/kbi6 pta5 (1) /rst /kbi5 pta4 (1) /ad4/kbi4 pta3 (1) /ad3/kbi3 pta2 (1) /ad2/kbi2 pta1 (1) /ad1/kbi1 pta0 (1) /ad0/kbi0 ptb7/v out /ad6/fault (2) ptb6/v? ptb5/v+ ptb4/pwm1 ptb3/pwm0 ptb2/fault (2) ptb1/bot ptb0/top ptc1 (1) /osc2 ptc0 (1) /osc1 power v ss v dd ddra porta ptc2 (1) /shtdwn/irq flash programming oscillator cpu registers arithmetic/logic unit (alu) system integration module dual channel pwm module high resolution pwm module low-voltage inhibit module computer operating properly module 2-channel timer module 8-bit analog-to-digital converter module op amp/comparator module keyboard interrupt module module routines rom ? 674 bytes registers ? 64 bytes 1. pin contains integrated pullup device. 2. fault function switchable between pins ptb2 and ptb7. notes: features mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 141 figure 15-2. pwm module block diagram addr. register name bit 7 6 5 4 3 2 1 bit 0 $0040 pwm control register 1 (pctl1) see page 153. read: 0 fpos pwmint pwmf 00 ldok pwmen write: reset: 0 0 0 0 0 0 0 0 $0041 pwm control register 2 (pctl2) see page 155. read: ldfq1 ldfq0 dis1 dis0 pol1 pol0 prsc1 prsc0 write: reset: 0 0 0 0 1 1 0 0 $0042 fault control register (fcr) see page 157. read: 0 0 0 0 0 0 fint fmode write: reset: 0 0 0 0 0 0 0 0 $0043 fault status register (fsr) see page 157. read: 0 0 0 0 0 0 fpin fflag write: reset: u 0 u 0 u 0 u 0 $0044 fault control register 2 (fcr2) see page 158. read: 0 0 0 0 0 0 0 0 write: ftack reset: 0 0 0 0 0 0 0 0 r = reserved bold = buffered figure 15-3. register summary pwm0 pin pwm1 pin timebase cpu bus output control fault interrupt pin 12 control logic block 8 pwm channels 1 and 2 fault protection pulse width modulator with fault input (pwm) mc68hc908lb8 data sheet, rev. 0 142 freescale semiconductor 15.3 timebase this section provides a discussion of the timebase. 15.3.1 resolution for edge-aligned mode, a 12-bit up-onl y counter is used to create the pwm period. therefore, the pwm resolution in edge-aligned mode is one clock (highest resolution is 125 ns @ busclk = 8 mhz) as shown $0045 pwm counter register high (pcnth) see page 151. read: 0 0 0 0 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $0046 pwm counter register low (pcntl) see page 151. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $0047 pwm counter modulo register high (pmodh) see page 152. read: 0 0 0 0 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 indeterminate after reset $0048 pwm counter modulo register low (pmodl) see page 152. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset $0049 pwm 0 value register high (pval0h) see page 152. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $004a pwm 0 value register low (pval0l) see page 153. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $004b pwm 1 value register high (pval1h) see page 152. read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset: 0 0 0 0 0 0 0 0 $004c pwm 1 value register low (pval1l) see page 153. read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: 0 0 0 0 0 0 0 0 $004d pwm disable mapping write once register (dismap) see page 156. read: 0 0 0 0 0 0 map1 map0 write: reset: 0 0 0 0 0 0 1 1 addr. register name bit 7 6 5 4 3 2 1 bit 0 r = reserved bold = buffered figure 15-3. register summary (continued) timebase mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 143 in figure 15-4 . again, the timer modulus register is used to determine the maximum count. the pwm period will equal: (timer modulus) x (pwm clock period) figure 15-4. edge-aligned pwm (positive polarity) 15.3.2 prescaler to permit lower pwm frequencies, a prescaler is prov ided which will divide the pwm clock frequency by 1, 2, 4, or 8. table 15-1 shows how setting the prescaler bits in pwm control register 2 affects the pwm clock frequency. this prescaler is buffered and will not be used by the pwm generator until the ldok bit is set and a new pwm reload cycle begins. up-only counter modulus = 4 pwm = 0 pwm = 1 pwm = 2 pwm = 3 pwm = 4 period = 4 x (pwm clock period) pulse width modulator with fault input (pwm) mc68hc908lb8 data sheet, rev. 0 144 freescale semiconductor 15.4 pwm generators pulse-width modulator (pwm) generators are discussed in this subsection. 15.4.1 load operation to help avoid erroneous pulse widths and pwm periods, the modulus, prescaler, and pwm value registers are buffered. new pwm values, counter mo dulus values, and prescalers can be loaded from their buffers into the pwm module every one, two, four, or eight pwm cycles. ldfq1 and ldfq0 in pwm control register 2 are used to control this reload frequency, as shown in table 15-2 . when a reload cycle arrives, regardless of whether an actual reload occu rs (as determined by the ldok bit), the pwm reload flag bit in pwm control register 1 will be set. if the pwmint bit in pwm control register 1 is set, a cpu interrupt request will be generated when pwmf is set. software can use this interrupt to calculate new pwm parameters in real time for the pwm module. table 15-1. pwm prescaler prescaler bits prsc1 and prsc0 pwm clock frequency 00 busclk 01 busclk/2 10 busclk/4 11 busclk/8 table 15-2. pwm reload frequency reload frequency bits ldfq1 and ldfq0 pwm reload frequency 00 every pwm cycle 01 every 2 pwm cycles 10 every 4 pwm cycles 11 every 8 pwm cycles pwm generators mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 145 for ease of software, the ldfqx bits are buffered. when the ldfqx bits are changed, the reload frequency will not change until the previous reload cycle is completed. see figure 15-5 . note when reading the ldfqx bits, the value is the buffered value (for example, not necessarily the value being acted upon). figure 15-5. reload frequency change pwmint enables cpu interrupt requests as shown in figure 15-6 . when this bit is set, cpu interrupt requests are generated when the pwmf bit is set. when the pwmint bit is clear, pwm interrupt requests are inhibited. pwm reloads will still occur at the reload rate, but no interrupt requests will be generated. figure 15-6. pwm interrupt requests to prevent a partial reload of pwm parameters from occurring while the software is still calculating them, an interlock bit controlled from so ftware is provided. this bit informs the pwm module that all the pwm parameters have been calculated, and it is ?okay? to use them. a new modulus, prescaler, and/or pwm value cannot be loaded into the pwm module until the ldok bit in pwm control register 1 is set. when the ldok bit is set, these new values are loaded in to a second set of registers and used by the pwm generator at the beginning of the next pwm reload cycle as shown in figure 15-7 and figure 15-8 . after these values are loaded, the ldok bit is cleared. note when the pwm module is enabled (via th e pwmen bit), a load will occur if the ldok bit is set. even if it is not set, an interrupt will occur if the pwmint bit is set. to prevent this, the software should clear the pwmint bit before enabling the pwm module. note setting pwmen forces pwm1 and pwm0 to be inputs and the appropriately configured fault pin to be an output, overriding the data reload reload reload reload reload reload reload change reload frequency to every 4 cycles change reload frequency to every cycle latch v dd cpu interrupt reset d ck pwmint pwmf pwm reload read pwmf as 1, write pwmf as 0 or reset request pulse width modulator with fault input (pwm) mc68hc908lb8 data sheet, rev. 0 146 freescale semiconductor direction register. in order to read the states of the pins, the data direction register bit must be a 0. figure 15-7. edge-aligned pwm value loading figure 15-8. edge-aligned modulus loading 15.4.2 pwm data overflow and underflow conditions the pwm value registers are 16-bit registers. althou gh the counter is only 12 bits, the user may write a 16-bit signed value to a pwm value register. as shown in figure 15-4 , if the pwm value is less than or equal to zero, the pwm will be inactive for the entire period. conversely, if the pwm value is greater than or equal to the timer modulus, the pwm will be active for the entire period. refer to table 15-3 . ldok = 1 modulus = 3 pwm value = 1 ldok = 1 modulus = 3 pwm value = 2 up-only counter pwm ldfq1:ldfq0 = 00 (reload every cycle) ldok = 0 modulus = 3 pwm value = 2 ldok = 0 modulus = 3 pwm value = 1 ldok = 0 modulus = 3 pwm value = 1 pwmf set pwmf set pwmf set pwmf set pwmf set ldok = 1 modulus = 3 pwm value = 2 ldok = 1 modulus = 4 pwm value = 2 ldok = 1 modulus = 2 pwm value = 2 up-only counter pwm ldfq1:ldfq0 = 00 (reload every cycle) ldok = 0 modulus = 1 pwm value = 2 pwmf set pwmf set pwmf set pwmf set fault protection mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 147 note the terms ?active? and ?inactive? refer to the asserted and negated states of the pwm signals and should not be confused with the high-impedance state of the pwm pins. 15.4.3 output polarity the output polarity of the pwms is determined by the polx bits. positive polarity means that when the pwm is active, the pwm output is high. conversely , negative polarity means that when the pwm is active, pwm output is low. see figure 15-9 . figure 15-9. pwm output polarity 15.5 fault protection conditions may arise in the exter nal drive circuitry which require t hat the pwm signals become inactive immediately. furthermore, it may be desirable to selectively disable pwm(s) solely with software. one or more pwm pins can be disabled (forced to t heir inactive state) by applying a logic high to the external fault pin or by writing a logic high to either of the disabl e bits (dis0 and dis1 in pwm control register 1). figure 15-10 shows the structure of the pwm disa bling scheme. while the pwm pins are disabled, they are forced to their inactive state. the pwm generator continues a fault can also generate a cpu interrupt. the fault pin has its own interrupt vector. 15.5.1 fault condition input pin a logic high level on a fault pin disables the pw m(s) determined by the disable map bits (mapx). the external fault pin is software-configurable to re-ena ble the pwms either with the fault pin (automatic table 15-3. pwm data overflow and underflow conditions pwmvalxh:pwmvalxl condition pwm value used $0000?$0fff normal per register contents $1000?$7fff overflow $fff $8000?$ffff underflow $000 up-only counter modulus = 4 pwm <= 0 pwm = 1 pwm = 2 pwm = 3 pwm >= 4 edge-aligned positive polarity modulus = 4 pwm <= 0 pwm = 1 pwm = 2 pwm = 3 pwm >= 4 edge-aligned negative polarity pulse width modulator with fault input (pwm) mc68hc908lb8 data sheet, rev. 0 148 freescale semiconductor mode) or with software (manual mode). the fault pin has an associated fmode bit to control the pwm re-enabling method. automatic mode is selected by sett ing the fmode bit in the fault control register. manual mode is selected when fmode is clear. the operation of the fault pin is asnynchronous. if it is enabled by either the map0 or map1 disable bits and the fault pin goes high, the associated pwm(s) outputs are immediately disabled without waiting for the next bus cycle. the location of the fault pin is software configurable to one of two locations. enabling the fault functionality of a given pin does not disconnect that pin from any other module that is trying to use the pin. figure 15-10. pwm disabling scheme 15.5.1.1 automatic mode in automatic mode, the pwm(s) are disabled immediat ely once a fault condition is detected (logic high). the pwm(s) remain disabled until the fault conditi on is cleared (logic low) and a new pwm cycle begins as shown in figure 15-11 . clearing the fflag event bit will not enable the pwms in automatic mode. figure 15-11. pwm disabling in automatic mode the fault pin?s logic state is reflected in the fpin bit. any write to th is bit is overwritten by the pin state. the fflag event bit is set with each rising edge of t he fault pin. to clear the fflag bit, the user must write a 1 to the ftack bit. fault pin1 fint1 cycle start logic high for fault pwm disable fmode clear by writing 1 to ftack interrupt request shot sq r sq r one fflag manual mode auto mode fault pin disable note: in manual mode (fmode = 0), fault may be cleared only if a logic level low at the input of the fault pin is present. pwm(s) enabled pwm(s) enabled pwm(s) disabled (inactive) fault pin fault protection mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 149 if the fint bit is set, a fault condition resulting in se tting the fflag bit will also latch a cpu interrupt request. the interrupt request latch is no t cleared until one of these actions occurs: the fflag bit is cleared by writing a 1 to the corresponding ftack bit. the fint bit is cleared. this will not clear the fflag bit. a reset automatically cl ears the interrupt latch. if prior to a vector fetch, the interrupt request latch is cleared by one of the actions listed, a cpu interrupt will no longer be requested. a vector fetch does not alter the state of the pwms, the fflag event flag, or fint. note if the fflag or fint bits are not cleared during the interrupt service routine, the interrupt request latch will not be cleared. 15.5.1.2 manual mode in manual mode, the pwm(s) are disabled immediately once a fault condition is detected (logic high). the pwm(s) remain disabled until software clears th e fflag event bit and a new pwm cycle begins. a fault condition on the pin can only be cleared, allowing the pwm(s) to enable, if a logic low level at the fault pin is present at the start of a pwm cycle. see figure 15-12 . the function of the fault control and event bits is the same as in automatic mode except that the pwms are not re-enabled until the fflag event bit is clear ed by writing to the ftack bit and the fault condition is cleared (logic low). figure 15-12. pwm disabling in manual mode 15.5.2 software output disable setting pwm disable bit dis0 or dis1 in pwm control register 1 immediately disables the corresponding pwm pins. the pwm pin(s) remain disabled until t he pwm disable bit is cleared and a new pwm cycle begins as shown in figure 15-13 . setting a pwm disable bit does not latch a cpu interrupt request, and there are no event flags associated with the pwm disable bits. pwm(s) enabled pwm(s) enabled pwm(s) disabled fflagx cleared fault pin 2 or 4 pulse width modulator with fault input (pwm) mc68hc908lb8 data sheet, rev. 0 150 freescale semiconductor 15.6 initialization and the pwmen bit for proper operation, all registers should be initia lized and the ldok bit should be set before enabling the pwm via the pwmen bit. when the pwmen bit is fi rst set, a reload will occur immediately, setting the pwmf flag and generating an interrupt if pwmint is set. note if the ldok bit is not set when pwmen is set after a reset , the prescaler and pwm values will be 0, but the modulus will be unknown. if the ldok bit is not set after the pwmen bit has been cleared then set (without a reset ), the modulus value that was last loaded will be used. because of the equals-comparator architecture of this pwm, the modulus = 0 case is considered illegal. therefore, the modulus register is not reset, and a modulus value of 0 will result in waveforms inconsistent with the other modulus waveforms. see 15.8.2 pwm counter modulo registers . when pwmen is set, the pwm pins change from high impedance to outputs. at this time, assuming no fault condition is present, the pwm pins will drive according to the pwm values and polarity. see the timing diagram in figure 15-13 . figure 15-13. pwmen and pwm pins when the pwmen bit is cleared, this will occur: pwm pins will be three-stated pwm counter is cleared and will not be clocked internally, the pwm generator will force its output s to 0 to avoid glitches when the pwmen is set again when pwmen is cleared, all fault circuitry remains active. note the pwmf flag and pending cpu interrupts are not cleared when pwmen = 0. 15.7 pwm operation in low-power modes 15.7.1 wait mode when the microcontroller is put in low-power wait mode via the wait instruction, all clocks to the pwm module will continue to run. if an interrupt is issued from the pwm module (via a reload or a fault), the microcontroller will exit wait mode. cpu clock pwmen pwm pins drive according to pwm value and polarity port function port function control logic block mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 151 clearing the pwmen bit before entering wait mode wi ll reduce power consumption in wait mode because the counter, prescaler divider, and ldfq divider wi ll no longer be clocked. in addition, power will be reduced because the pwms will no longer toggle. 15.7.2 stop mode when the microcontroller is put into stop mode via t he stop instruction, the pwm will stop functioning. the pwm0 and pwm1 outputs are set to logic 0. the stop instruction does not affect the register conditions or the state of the pwm counters. when th e mcu exits stop mode after an external interrupt the pwm resumes operation. 15.8 control logic block this subsection provides a description of the control logic block. 15.8.1 pwm counter registers the pwm counter registers (pcnth and pcntl) disp lay the 12-bit up-only counter. when the high byte of the counter is read, the lower byte is latched. pcntl will hold this latched value until it is read. see figure 15-14 and figure 15-15 . 15.8.2 pwm counte r modulo registers the pwm counter modulus registers (pmodh and pmodl) hold a 12-bit unsigned number that determines the maximum count for the up-only co unter. the pwm period will equal the modulus. see figure 15-16 and figure 15-17 . address: $0045 bit 7654321bit 0 read:0000bit 11bit 10bit 9bit 8 write: reset:00000000 = unimplemented figure 15-14. pwm counter register high (pcnth) address: $0046 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 = unimplemented figure 15-15. pwm counter register low (pcntl) pulse width modulator with fault input (pwm) mc68hc908lb8 data sheet, rev. 0 152 freescale semiconductor to avoid erroneous pwm periods, this value is buffer ed and will not be used by the pwm generator until the ldok bit has been set and th e next pwm load cycle begins. note when reading this register, the value read is the buffer (not necessarily the value the pwm generator is currently using). because of the equals-comparator architecture of this pwm, the modulus = 0 case is considered illegal. therefore, the modulus register is not reset, and a modulus value of 0 will result in waveforms inconsistent with the other modulus waveforms. if a modulus of 0 is loaded, the counter will continually count down from $fff. this operation will not be tested or guaranteed (the user should consider it illegal). howe ver, the fault condi tions will still be guaranteed. 15.8.3 pwmx value registers each of the two pwms has a 16-bit pwm value register. address: $0047 bit 7654321bit 0 read:0000 bit 11 bit 10 bit 9 bit 8 write: reset:0000 indeterminate after reset = unimplemented figure 15-16. pwm counter modulo register high (pmodh) address: $0048 bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset: indeterminate after reset figure 15-17. pwm counter modulo register low (pmodl) bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 bold = buffered figure 15-18. pwmx value registers high (pvalxh) control logic block mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 153 the 16-bit signed value stored in this register determi nes the duty cycle of the pwm. the duty cycle is defined as: (pwm value/modulus) x 100 writing a number less than or equal to 0 causes the pwm to be off for the entire pwm period. writing a number greater than or equal to the 12-bit modulus causes the pwm to be on for the entire pwm period. to avoid erroneous pwm pulses, this value is buffe red and will not be used by the pwm generator until the ldok bit has been set and th e next pwm load cycle begins. note when reading these registers, the value read is the buffer (not necessarily the value the pwm generator is currently using). 15.8.4 pwm control register 1 pwm control register 1 (pctl1) controls pwm enabling/ disabling, the location of the pwm fault bit, the loading of new modulus, prescaler, pwm values, and the pwm correction method. fpos ? fault pin position bit this read/write bit allows the user to select the location of the fault pin. 1 = fault pin functionality is placed on ptb2 0 = fault pin functionality is placed on ptb7 note placing the fault pin on ptb7 will not affect the adc or the op amp/comparator connections. this is to allow the output of the op amp/comparator to be used as the input to the fault pin and for this same signal to be simultaneously measured by the adc. pwmint ? pwm interrupt enable bit this read/write bit allows the user to enable and disable pwm cpu interrupts. if set, a cpu interrupt will be pending when the pwmf flag is set. 1 = enable pwm cpu interrupts 0 = disable pwm cpu interrupts bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 bold = buffered figure 15-19. pwmx value registers low (pvalxl) address: $0040 bit 7654321bit 0 read: 0 fpos pwmint pwmf 00 ldok pwmen write: reset:00000000 = unimplemented figure 15-20. pwm control register 1 (pctl1) pulse width modulator with fault input (pwm) mc68hc908lb8 data sheet, rev. 0 154 freescale semiconductor note when pwmint is cleared, pending cpu interrupts are inhibited. pwmf ? pwm reload flag this read/write bit is set at the beginning of every reload cycle regardless of the state of the ldok bit. this bit is cleared by reading pwm control register 1 with the pwmf flag set, then writing a 0 to pwmf. if another reload occurs before the clearing sequen ce is complete, then writing 0 to pwmf has no effect. 1 = new reload cycle began 0 = new reload cycle has not begun note when pwmf is cleared, pending pwm cpu interrupts are cleared (not including fault interrupts). ldok? load ok bit this read/write bit loads the prescaler bits of the pmctl2 register and the entire pmmodh/l and pwmvalh/l registers into a set of buffers. the buffered prescaler divisor, pwm counter modulus value, and pwm pulse will take effect at the next pw m load. set ldok by reading it when it is 0 and then writing a 1 to it. ldok is automatically cleared after the new values are loaded or can be manually cleared before a reload by writing a 0 to it. reset clears ldok. 1 = load prescaler, modulus, and pwm values 0 = do not load new modulus, prescaler, and pwm values note the user should initialize the pwm registers and set the ldok bit before enabling the pwm. a pwm cpu interrupt request can still be generated when ldok is 0. pwmen ? pwm module enable bit this read/write bit enables and disables the pwm generator and the pwm pins. when pwmen is clear, the pwm generator is disabled and the pwm pins are in the high-impedance state. when the pwmen bit is set, the pwm generator and pwm pins are activated. for more information, see 15.6 initialization and the pwmen bit . 1 = pwm generator and pwm pins enabled 0 = pwm generator and pwm pins disabled 15.8.5 pwm control register 2 pwm control register 2 (pctl2) controls the pwm lo ad frequency, pwm channel enabling/disabling, the pwm polarity, the pwm correction method, and the pwm counter prescaler. for ease of software and to avoid erroneous pwm periods, some of these register bits are buffered. the pwm generator will not use the prescaler value until the ldok bit has been set, and a new pwm cycle is starting. the load frequency bits are not used until the current load cycle is complete. see figure 15-21 . note the user should initialize this register before enabling the pwm. control logic block mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 155 ldfq1 and ldfq0 ? pwm load frequency bits these buffered read/write bits select the pwm cpu load frequency according to table 15-4 . note when reading these bits, the value read is the buffer value (not necessarily the value the pwm generator is currently using). the ldfqx bits take effect when the current load cycle is complete regardless of the state of the load okay bit, ldok. note reading the ldfqx bit reads the buffe red values and not necessarily the values currently in effect. dis1 ? software disable bit for pwm1 this read/write bit allows the user to disable pin pwm1. 1 = disable pwm1 0 = re-enable pwm1 dis0 ? software disable bit for pwm0 this read/write bit allows the user to disable pin pwm0. 1 = disable pwm0 0 = re-enable pwm0 pol1 ? polarity bit for pwm1 this read/write bit selects the polarity of the pwm waveform of pwm1. positive polarity means that when the pwm is active the pwm output is high. conversely, negative polarity means that when the pwm is active the pwm output is low. 1 = pwm1 has positive polarity 0 = pwm1 has negative polarity address: $0041 bit 7654321bit 0 read: ldfq1 ldfq0 dis1 dis0 pol1 pol0 prsc1 prsc0 write: reset:00001100 bold = buffered figure 15-21. pwm control register 2 (pctl2) table 15-4. pwm reload frequency reload frequency bits ldfq1 and ldfq0 pwm reload frequency 00 every pwm cycle 01 every 2 pwm cycles 10 every 4 pwm cycles 11 every 8 pwm cycles pulse width modulator with fault input (pwm) mc68hc908lb8 data sheet, rev. 0 156 freescale semiconductor pol0 ? this read/write bit selects the polarity of the pwm waveform of pwm1. positive polarity means that when the pwm is active the pwm output is high. conversely, negative polarity means that when the pwm is active the pwm output is low. 1 = pwm0 has positive polarity 0 = pwm0 has negative polarity prsc1 and prsc0 ? pwm prescaler bits these buffered read/write bits allow the pwm clock frequency to be modified as shown in table 15-5 . note when reading these bits, the value read is the buffer value (not necessarily the value the pwm generator is currently using). 15.8.6 pwm disable mappi ng write-once register the pwm disable mapping write-once register (dismap) contains two bits that control the pwm pins that will be disabled if an external fault occurs. after th is register is written for the first time, it cannot be rewritten unless a reset occurs. map1 ? disable map for pwm1 bit this write-once bit allows the user to select pwm1 to be disabled when a logic 1 is present on the fault pin. 1 = disables pwm1 when an external fault occurs 0 = prevents pwm1 from being disabled by hardware map0 ? disable map for pwm0 bit this write-once bit allows the user to select pwm0 to be disabled when a logic 1 is present on the fault pin. 1 = disables pwm0 when an external fault occurs 0 = prevents pwm0 from being disabled by hardware table 15-5. pwm prescaler prescaler bits prsc1 and prsc0 pwm clock frequency 00 busclk 01 busclk/2 10 busclk/4 11 busclk/8 address: $004d bit 7654321bit 0 read:000000 map1 map0 write: reset:00000011 = unimplemented figure 15-22. pwm disable mapping write-once register (dismap) control logic block mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 157 15.8.7 fault control register the fault control register (fcr) controls the fault-protection circuitry. fint ? fault interrupt enable bit this read/write bit allows the cpu interrupt caused by faults on the fault pin to be enabled. the fault protection circuitry is independent of this bit and will always be active. if a fault is detected, the pwm pins will still be disabled accordi ng to the disable mapping register. 1 = fault pin will cause cpu interrupts 0 = fault pin will not cause cpu interrupts fmode ? fault mode selection for fault pin bit (automatic versus manual mode) this read/write bit allows the user to select between automatic and manual mode faults. for further descriptions of each mode, see 15.5 fault protection . 1 = automatic mode 0 = manual mode 15.8.8 fault status register the fault status register (fsr) is a read-only register that indicates the current fault status. fpin ? state of fault pin bit this read-only bit allows the user to read the current state of the fault pin. 1 = fault pin is at logic 1 0 = fault pin is at logic 0 fflag ? fault event flag the fflag event bit is set immediately when a rising edge is seen on the fault pin. to clear the fflag bit, the user must write a 1 to the ftack bit in the fault acknowledge register. 1 = a fault has occurred on the fault pin 0 = no new fault on the fault pin address: $0042 bit 7654321bit 0 read:000000 fint fmode write: reset:00000000 = unimplemented figure 15-23. fault control register (fcr) address: $0043 bit 7654321bit 0 read:000000fpinfflag write: reset:000000u0 = unimplemented u = unaffected figure 15-24. fault status register (fsr) pulse width modulator with fault input (pwm) mc68hc908lb8 data sheet, rev. 0 158 freescale semiconductor 15.8.9 fault control register 2 the fault control register 2 (fcr2) is used to acknowledge and clear the fflag. ftack ? fault acknowledge bit the ftack bit is used to acknowledge and clear fflag. this bit will always read 0. writing a 1 to this bit will clear fflag. writing a 0 will have no effect. 15.9 pwm glossary cpu cycle one internal bus cycle (1/busclk) pwm clock cycle (or period) one tick of the pwm counter (1/busclk with no prescaler). see figure 15-26 . pwm cycle (or period) edge-aligned mode: the time it takes the pwm counter to count up (modulus/busclk). see figure 15-26 . figure 15-26. pwm clock cycle and pwm cycle definition address: $0044 bit 7654321bit 0 read:00000000 write: ftack reset:00000000 = unimplemented figure 15-25. fault control register (fcr2) pwm pwm cycle (or period) clock cycle edge-aligned mode pwm glossary mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 159 pwm load frequency frequency at which new pwm parameters get loaded into the pwm. see figure 15-27 . figure 15-27. pwm load cycle/frequency definition reload new modulus, prescaler, & pwm values if ldok = 1 reload new modulus, prescaler, & pwm values if ldok = 1 pwm load cycle ldfq1:ldfq0 = 01 ? reload every two cycles (1/pwm load frequency) pulse width modulator with fault input (pwm) mc68hc908lb8 data sheet, rev. 0 160 freescale semiconductor mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 161 chapter 16 resets and interrupts 16.1 introduction resets and interrupts are responses to exceptional event s during program execution. a reset re-initializes the microcontroller (mcu) to its startup condition. an interrupt vectors the program counter to a service routine. 16.2 resets a reset immediately returns the mcu to a known star tup condition and begins program execution from a user-defined memory location. 16.2.1 effects a reset: immediately stops the operation of the instruction being executed initializes certain control and status bits loads the program counter with a user-defin ed reset vector address from locations $ffff and $fffe 16.2.2 external reset a logic 0 applied to rst for a time, t irl , generates an external reset when pin pta5/rst /kb5 is configured as a reset pin. an external reset sets th e pin bit in the system integration module (sim) reset status register. 16.2.3 internal reset sources: power-on reset (por) computer operating properly (cop) low-power reset circuits illegal opcode illegal address 16.2.3.1 power-on reset (por) a power-on reset (por) is an internal reset caused by a positive transition on the v dd pin. v dd at the por must go below por rearm voltage (v por ) to reset the mcu. this distinguishes between a reset and a por. the por is not a brown-out detector, low-voltage detector, or glitch detector. a power-on reset: drives the rst pin low during the oscillator stabilization delay resets and interrupts mc68hc908lb8 data sheet, rev. 0 162 freescale semiconductor releases the rst pin 32 busclkx4 cycles after the oscillator stabilization delay sets the por bit in the sim reset status regi ster and clears all other bits in the register figure 16-1. power-on reset recovery 16.2.3.2 computer operating properly (cop) reset a computer operating properly (cop) reset is an intern al reset caused by an overflow of the cop counter. a cop reset sets the cop bit in the sim reset status register. to clear the cop counter and prevent a cop reset, write any value to the cop control register at location $ffff. 16.2.3.3 low-voltage inhibit (lvi) reset a low-voltage inhibit (lvi) reset is an internal reset caused by a drop in the power supply voltage to the lvi tripf voltage. an lvi reset: holds the clocks to the cpu and modules inactive for an oscill ator stabilization delay of 4096 busclkx4 cycles after the power supply voltage rises to the lvi tripf voltage drives the rst pin low for as long as v dd is below the lvi tripf voltage and during the oscillator stabilization delay sets the lvi bit in the sim reset status register 16.2.3.4 illegal opcode reset an illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set. an illegal opcode reset sets the ilop bit in the sim reset status register. if the stop enable bit, stop, in the config1 register is a 0, the stop instruction causes an illegal opcode reset. 16.2.3.5 illegal address reset an illegal address reset is an internal reset caused by opcode fetch from an unmapped address. an illegal address reset sets the ilad bit in the sim reset status register. a data fetch from an unmapped address does not generate a reset. porrst (1) osc1 busclkx4 busclkx2 rst pin 4096 cycles 32 cycles 1. porrst is an internally generated power-on reset pulse. resets mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 163 16.2.4 system integration modu le (sim) reset status register this read-only register contains flags to show rese t sources. all flag bits are automatically cleared following a read of the register. reset service can read the sim reset status register to clear the register after power-on reset and to determine the source of any subsequent reset. the register is initialized on power-up as shown with the por bit set and all other bits cleared. during a por or any other internal reset, the rst pin is pulled low as long as pin pta5/rst /kb5 is configured for reset operation. note only a read of the sim reset status register clears all reset flags. after multiple resets from different sources without reading the register, multiple flags remain set. por ? power-on reset flag 1 = power-on reset since last read of srsr 0 = read of srsr since last power-on reset pin ? external reset flag 1 = external reset via rst pin since last read of srsr 0 = por or read of srsr since last external reset cop ? computer operating properly reset bit 1 = last reset caused by timeout of cop counter 0 = por or read of srsr since any reset ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr since any reset ilad ? illegal address reset bit 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr since any reset modrst ? monitor mode entry module reset bit 1 = last reset caused by forced monitor mode entry. 0 = por or read of srsr since any reset lvi ? low-voltage inhibit reset bit 1 = last reset caused by low-power supply voltage 0 = por or read of srsr since any reset address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 = unimplemented figure 16-2. sim reset status register (srsr) resets and interrupts mc68hc908lb8 data sheet, rev. 0 164 freescale semiconductor 16.3 interrupts an interrupt temporarily changes the sequence of progr am execution to respond to a particular event. an interrupt does not stop the operation of the instruction being executed, but begins when the current instruction completes its operation. 16.3.1 effects an interrupt: saves the cpu registers on the stack. at the end of the interrupt, the rti instruction recovers the cpu registers from the stack so that normal processing can resume. sets the interrupt mask (i bit) to prevent additional interrupts. once an interrupt is latched, no other interrupt can take precedence, regardless of its priority. loads the program counter with a user-defined vector address after every instruction, the cpu checks all pending interrupts if the i bit is not set. if more than one interrupt is pending when an instruction is done, the hi ghest priority interrupt is serviced first. in the example shown in figure 16-4 , if an interrupt is pending upon exit from the interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. figure 16-3. interrupt stacking order condition code register accumulator index register (low byte) (1) program counter (high byte) program counter (low byte) 1 2 3 4 5 5 4 3 2 1 stacking order 1. high byte of index register is not stacked. $00ff default address on reset unstacking order interrupts mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 165 figure 16-4 . interrupt recognition example the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note to maintain compatibility with the m6805 family, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses th e indexed addressing mode, save the h register and then restore it prior to exiting the routine. see figure 16-5 for a flowchart depicting interrupt processing. 16.3.2 sources the sources in table 16-1 can generate cpu interrupt requests. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine resets and interrupts mc68hc908lb8 data sheet, rev. 0 166 freescale semiconductor table 16-1. interrupt sources source flag mask (1) notes: 1. the i bit in the condition code register is a global mask for all interrupt sources except the swi instruction. priority (2) 2. 0 = highest priority vector address reset none none 0 $ffff?$fffe swi instruct ion none none 1 $fffd?$fffc irq pin irqf imask 2 $fffa?$fffb tim channel 0 ch0f ch0ie 3 $fff7?$fff6 tim channel 1 ch1f ch1ie 4 $fff5?$fff4 tim overflow tof toie 5 $fff3?$fff2 fault interrupt (pwm) fflag fint 6 $fff1?$fff0 pwmint interrupt (pwm) pwmint wpmf 7 $ffef?$ffee shtdwn interrupt shtif shtien 8 $ffed?$ffec keyboard pin keyf imaskk 9 $ffe1?$ffe0 adc conversion complete coco aien 10 $ffdf-$ffde interrupts mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 167 figure 16-5. interrupt processing 16.3.2.1 software interrupt (swi) instruction the software interrupt (swi) instruction causes a non-maskable interrupt. no no no yes no no yes no yes yes from reset break i bit set? irq interrupt cgm interrupt fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes yes i bit set? interrupt yes other interrupts no swi instruction rti instruction ? ? ? ? ? ? resets and interrupts mc68hc908lb8 data sheet, rev. 0 168 freescale semiconductor note a software interrupt pushes pc onto the stack. an swi does not push pc ? 1, as a hardware interrupt does. 16.3.2.2 break interrupt the break module causes the cpu to execute an sw i instruction at a software-programmable break point. 16.3.2.3 irq pin a logic 0 on the irq pin latches an external interrupt request when pin ptc2/shtdwn/irq is configured as a software interrupt. 16.3.2.4 timer interface module (tim) tim cpu interrupt sources: tim overflow flag (tof) ? the tof bit is set when the tim counter value rolls over to $0000 after matching the value in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim status and control register. tim channel flags (ch1f?ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. the channel x interrupt enable bit, chxie, enables channel x tim cpu interrupt requests. chxf and chxie are in the tim channel x status and control register. 16.3.2.5 kbd0?kbd6 pins a logic 0 on a keyboard interrupt pin latches an external interrupt request. 16.3.2.6 analog-to-digital converter (adc) when the aien bit is set, the adc module is capable of generating a cpu interrupt after each adc conversion. the coco bit is not used as a conversion complete flag when interrupts are enabled. 16.3.2.7 pulse-width modulator with fault input (pwm) pwm cpu interrupt sources: fault pin interrupt (fault) ? when the fint bit is set, the pwm module is capable of generating a cpu interrupt on detection of a rising edge on the fault pin. pwm interrupt (pwmint) ? when the pwmint bit is set, the pwm module is capable of generating a cpu interrupt when the pwm reload flag (pwmf) is set. the pwmf bit is set at the beginning of every reload cycle. 16.3.2.8 high resolution pwm (hrp) when the shtie bit is set, the hrp module is capable of generating a cpu interrupt on detection of a falling edge or a low level on the shtdn pin. mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 169 chapter 17 system integration module (sim) 17.1 introduction this section describes the system integration module (sim). together with the central processor unit (cpu), the sim controls all microcontroller unit (mcu) activities. a block diagram of the sim is shown in figure 17-1 . table 17-1 is a summary of the sim input/output (i/o) registers. the sim is a system state controller that coordinates cpu and exception timing. the sim is responsible for: bus clock generation and control for cpu and peripherals: ? stop/wait/reset/break entry and recovery ? internal clock control master reset control, including power-on reset (por) and computer operating properly (cop) timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture expandable to 128 interrupt sources table 17-1 shows the internal signal names used in this section. system integration module (sim) mc68hc908lb8 data sheet, rev. 0 170 freescale semiconductor figure 17-1. sim block diagram table 17-1. signal name conventions signal name description busclkx4 buffered clock from the internal, rc or xtal oscillator circuit. busclkx2 the busclkx4 frequency divided by two. this signal is again divided by two in the sim to generate the internal bus clocks (bus clock = busclkx4 4). iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to osc) busclkx2 (from osc) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter busclkx4 (from osc) 2 v dd internal pullup device forced monitor mode entry cop clock sim bus clock control and generation mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 171 17.2 sim bus clock control and generation the bus clock generator provides system clock signa ls for the cpu and peripherals on the mcu. the system clocks are generated from an incoming clock, busclkx2, as shown in figure 17-3 . figure 17-3. sim clock signals 17.2.1 bus timing in user mode , the internal bus frequency is the oscillat or frequency (busclkx4) divided by four. 17.2.2 clock star t-up from por when the power-on reset module generates a reset, th e clocks to the cpu and peripherals are inactive and held in an inactive phase until after the 4096 busclkx4 cycle por time out has completed. the rst pin is driven low by the sim during this entire per iod. the ibus clocks start upon completion of the time out. 17.2.3 clocks in stop mode and wait mode upon exit from stop mode by an interrupt or reset, the sim allows busclkx4 to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay time out. this time out is selectable as 4096 or 32 busclkx4 cycles. see 17.6.2 stop mode . addr.register name bit 7654321bit 0 $fe00 break status register (bsr) see page 181. read: rrrrrr sbsw r write: note (1) reset:00000000 1. writing a 0 clears sbsw. $fe01 sim reset status register (srsr) see page 182. read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 $fe03 break flag control register (bfcr) see page 183. read: bcferrrrrrr write: reset: 0 = unimplemented r = reserved figure 17-2. sim i/o register summary 2 bus clock generators sim sim counter from oscillator from oscillator busclkx2 busclkx4 system integration module (sim) mc68hc908lb8 data sheet, rev. 0 172 freescale semiconductor in wait mode, the cpu clocks are inactive. the sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to s ee if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. 17.3 reset and s ystem initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating properly module (cop) low-voltage inhibit module (lvi) illegal opcode illegal address forced monitor mode entry reset (modrst) all of these resets produce the vector $fffe:$ffff ($fefe:$feff in monitor mode) and assert the internal reset signal (irst). irst causes all register s to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 17.4 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the sim reset status register (srsr). see 17.7 sim registers. 17.3.1 external pin reset the rst pin circuit includes an internal pullu p device. pulling the asynchronous rst pin low halts all processing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 busclkx4 cycles, assuming that neither the por nor the lvi was the source of the reset. see table 17-2 for details. figure 17-4 shows the relative timing. figure 17-4. external reset timing 17.3.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 busclkx4 cycles to allow resetting of external peripherals. the internal reset signal irst continues to be asserted for an additional 32 cycles. table 17-2. pin bit set timing reset type number of cycl es required to set pin por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l busclkx2 reset and system initialization mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 173 see figure 17-5 . an internal reset can be caused by an ille gal address, illegal opcode, cop timeout, lvi, or por. see figure 17-6 . note for lvi or por resets, the sim cycles through 4096 + 32 busclkx4 cycles during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 17-5 . figure 17-5. internal reset timing the cop reset is asynchronous to the bus clock. figure 17-6. sources of internal reset the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. 17.3.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 + 32 busclkx4 cycles. thirty-two busclkx4 cy cles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, these events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables the oscillator to drive busclkx4. internal clocks to the cpu and modules are hel d inactive for 4096 busclkx4 cycles to allow stabilization of the oscillator. the rst pin is driven low during the oscillator stabilization time. the por bit of the sim reset status register (srs r) is set and all other bits in the register are cleared. irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high busclkx4 illegal address rst illegal opcode rst coprst lvi por internal reset modrst system integration module (sim) mc68hc908lb8 data sheet, rev. 0 174 freescale semiconductor figure 17-7. por recovery 17.3.2.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of th e cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all internal reset sources. the cop module is disabled if the irq pin is held at v tst while the mcu is in monitor mode. the cop module can be disabled only through combinational l ogic conditioned with the high voltage signal on the irq pin. this prevents the cop from becoming disabled as a result of external noise. 17.3.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the sim reset status register (srsr) and causes a reset. if the stop enable bit, stop, in the mask option register is 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode re set. the sim actively pulls down the rst pin for all internal reset sources. 17.3.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the sim reset status register (srsr) and resetting the mcu. a data fetch from an unmapped add ress does not generate a reset. the sim actively pulls down the rst pin for all internal reset sources. 17.3.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit module (lvi) asserts its output to the sim when the v dd voltage falls to the lvi tripf voltage. the lvi bit in the sim reset status r egister (srsr) is set, and the external reset pin (rst ) is held low while the sim counter counts out 4 096 + 32 busclkx4 cycles. thirty-two busclkx4 porrst osc1 busclkx4 busclkx2 rst iab 4096 cycles 32 cycles $fffe $ffff sim counter mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 175 cycles later, the cpu is released from reset to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 17.3.2.6 monitor mode entry module reset (modrst) the monitor mode entry module reset (modrst) asserts its output to the sim when monitor mode is entered in the condition where the reset vectors are erased ($ff). when modrst gets asserted, an internal reset occurs. the sim actively pulls down the rst pin for all internal reset sources. 17.4 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter is 13 bits long. 17.4.1 sim counter du ring power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initializ ed, it enables the clock generation module (cgm) to drive the bus clock state machine. 17.4.2 sim counter du ring stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt, break, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the mask option register. if the ssrec bit is a 1, then the stop recovery is reduced from the normal delay of 4096 busclkx4 cycles down to 32 busclkx4 cycles. this is ideal for applications using canned oscillators that do not require long startup times from stop mode. external crystal applications should use the full stop recovery time, that is, with ssrec cleared. 17.4.3 sim counter and reset states external reset has no effect on the sim counter. see 17.6.2 stop mode for details. the sim counter is free-running after all reset states. see 17.3.2 active resets from internal sources for counter control and internal reset recovery sequences. 17.5 exception control normal, sequential program execution can be changed in three different ways: interrupts: ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts 17.5.1 interrupts at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 17-8 shows interrupt entry timing. figure 17-9 shows interrupt recovery timing. system integration module (sim) mc68hc908lb8 data sheet, rev. 0 176 freescale semiconductor figure 17-8 . interrupt entry timing figure 17-9. interrupt recovery timing interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the i bit is cleared). see figure 17-10 . 17.5.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 17-11 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1 [7:0] pc ? 1 [15:8] opcode operand i bit exception control mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 177 figure 17-10. interrupt processing no no yes no no yes no yes as many interrupts i bit set? from reset break i bit set? irq interrupt? swi instruction? rti instruction? fetch next instruction unstack cpu registers stack cpu registers set i bit load pc with interrupt vector execute instruction yes yes as exist on chip interrupt? system integration module (sim) mc68hc908lb8 data sheet, rev. 0 178 freescale semiconductor figure 17-11 . interrupt recognition example the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note to maintain compatibility with the m6805 family, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. 17.5.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 17.5.2 reset all reset sources always have equal and highest priority and cannot be arbitrated. 17.5.3 break interrupts the break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output (see 19.2 break module (brk) ). the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each module to see how each module is affected by the break state. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine low-power modes mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 179 17.5.4 status flag pr otection in break mode the sim controls whether status flags contained in other modules can be cleared during break mode. the user can select whether flags are protected from bei ng cleared by properly initializing the break clear flag enable bit (bcfe) in the sim break flag control register (sbfcr). protecting flags in break mode ensures that set fl ags will not be cleared while in break mode. this protection allows registers to be freely read and writ ten during break mode without losing status flag information. setting the bcfe bit enables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status fl ags with a 2-step clearing mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 17.6 low-power modes executing the wait or stop instruction puts the mcu in a low power-consumption mode for standby situations. the sim holds the cpu in a non-clocked st ate. the operation of each of these modes is described in the following subsections. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 17.6.1 wait mode in wait mode, the cpu clocks are inactive while the peripheral clocks continue to run. figure 17-12 shows the timing for wait mode entry. a module that is active during wait mode can wakeup the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wa it instruction during which the interrupt occurred. in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode also can be exited by a reset (or break in emulation mode). a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim br eak status register (sbsr ). if the cop disable bit, copd, in the mask option register is 0, then the computer operating properly module (cop) is enabled and remains active in wait mode. figure 17-13 and figure 17-14 show the timing for wait recovery. figure 17-12. wait mode entry timing wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. system integration module (sim) mc68hc908lb8 data sheet, rev. 0 180 freescale semiconductor figure 17-13. wait recovery from interrupt figure 17-14. wait recovery from internal reset 17.6.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset also caus es an exit from stop mode. the sim disables the clock generator module outputs (busclkx2 and busclkx4) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ssrec bit in the mask option register (mor). if ssrec is set, stop reco very is reduced from the normal delay of 4096 busclkx4 cycles down to 32. this is ideal for applications using canned oscillators that do not require long startup times from stop mode. note external crystal applications should use the full stop recovery time by clearing the ssrec bit. the sim counter is held in reset from the executi on of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 17-15 shows stop mode entry timing. figure 17-16 shows stop mode recovery time from interrupt or break. note to minimize stop current, all pins conf igured as inputs should be driven to a logic 1 or logic 0. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitsto pwait = rst pin or cpu interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 busclkx4 32 cycles 32 cycles sim registers mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 181 figure 17-15. stop mode entry timing figure 17-16. stop mode recovery from interrupt 17.7 sim registers the sim has three memory-mapped registers. table 17-3 shows the mapping of these registers. 17.7.1 break status register the break status register (bsr) contains a flag to i ndicate that a break caused an exit from wait mode. this register is only used in emulation mode. table 17-3. sim registers address register access mode $fe00 bsr user $fe01 srsr user $fe03 bfcr user address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset:00000000 r= reserved 1. writing a 0 clears sbsw. figure 17-17. break status register (bsr) stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. busclkx4 int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period system integration module (sim) mc68hc908lb8 data sheet, rev. 0 182 freescale semiconductor sbsw ? sim break stop/wait this status bit is useful in applications requiring a return to wait mode after exiting from a break interrupt. clear sbsw by writing a 0 to it. reset clears sbsw. 1 = wait mode was exited by break interrupt. 0 = wait mode was not exited by break interrupt. sbsw can be read within the break state swi routine. the user can modify t he return address on the stack by subtracting one from it. 17.7.2 sim reset status register this register contains six flags that show the source of the last reset provided all previous reset status bits have been cleared. clear the sim reset status register by reading it. a power-on reset sets the por bit and clears all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address reset bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr modrst ? monitor mode entry module reset bit 1 = last reset caused by monitor mode entry when vector locations $fffe and $ffff are $ff after por while irq = v dd 0 = por or read of srsr lvi ? low-voltage inhibit reset bit 1 = last reset caused by the lvi circuit 0 = por or read of srsr address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad modrst lvi 0 write: reset:10000000 = unimplemented figure 17-18. sim reset status register (srsr) sim registers mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 183 17.7.3 break flag control register the break control register contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 17-19. break flag control register (bfcr) system integration module (sim) mc68hc908lb8 data sheet, rev. 0 184 freescale semiconductor mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 185 chapter 18 timer interface module (tim) 18.1 introduction this section describes the timer interface (tim) module. the tim is a two-channel timer (only one of the channels is connected to an input/output pin) that prov ides a timing reference with input capture, output compare, and pulse-width-modulation (pwm) functions. figure 18-2 is a block diagram of the tim. figure 18-1. block diagram highlighting tim block and pins m68hc08 cpu control and status user flash ? 8 kbytes user ram ? 128 bytes monitor rom ? 350 bytes user flash vector space ? 34 bytes ddrb portb ddrc portc internal bus pta6 (1) /ad5/tch0/kbi6 pta5 (1) /rst /kbi5 pta4 (1) /ad4/kbi4 pta3 (1) /ad3/kbi3 pta2 (1) /ad2/kbi2 pta1 (1) /ad1/kbi1 pta0 (1) /ad0/kbi0 ptb7/v out /ad6/fault (2) ptb6/v? ptb5/v+ ptb4/pwm1 ptb3/pwm0 ptb2/fault (2) ptb1/bot ptb0/top ptc1 (1) /osc2 ptc0 (1) /osc1 power v ss v dd ddra porta ptc2 (1) /shtdwn/irq flash programming oscillator cpu registers arithmetic/logic unit (alu) system integration module dual channel pwm module high resolution pwm module low-voltage inhibit module computer operating properly module 2-channel timer module 8-bit analog-to-digital converter module op amp/comparator module keyboard interrupt module module routines rom ? 674 bytes registers ? 64 bytes 1. pin contains integrated pullup device. 2. fault function switchable between pins ptb2 and ptb7. notes: timer interface module (tim) mc68hc908lb8 data sheet, rev. 0 186 freescale semiconductor 18.2 features features of the tim include: one input capture/output compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse-width-modulation (pwm) signal generation programmable tim clock input with 7-frequenc y internal bus clock prescaler selection free-running or modulo up-count operation toggle any channel pin on overflow tim counter stop and reset bits figure 18-2. tim block diagram 18.3 functional description figure 18-2 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a mo dulo up-counter. the tim counter provides the timing reference for the input capture and output compare functions. the tim counter modulo registers, prescaler prescaler select internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus bus clock ms1a tch0 tch1 interrupt logic port logic interrupt logic interrupt logic port logic (not available on port pin) functional description mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 187 tmodh:tmodl, control the modulo value of the tim counter. software can read the tim counter value at any time without affecting the counting sequence. the two tim channels are programmable independently as input capture or output compare channels. if a channel is configured as input capture, then an in ternal pullup device may be enabled for that channel. . figure 18-3 summarizes the timer registers. addr.register name bit 7654321bit 0 $0020 timer status and control register (t1sc) see page 193. read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 timer counter register high (t1cnth) see page 194. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0022 timer counter register low (t1cntl) see page 194. read:bit 7654321bit 0 write: reset:00000000 $0023 timer counter modulo register high (t1modh) see page 195. read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0024 timer counter modulo register low (t1modl) see page 195. read: bit 7654321bit 0 write: reset:11111111 $0025 timer channel 0 status and control register (t1sc0) see page 196. read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 timer channel 0 register high (t1ch0h) see page 199. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0027 timer channel 0 register low (t1ch0l) see page 199. read: bit 7654321bit 0 write: reset: indeterminate after reset $0028 timer channel 1 status and control register (t1sc1) see page 196. read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 18-3. tim i/o register summary (sheet 1 of 2) timer interface module (tim) mc68hc908lb8 data sheet, rev. 0 188 freescale semiconductor 18.3.1 tim counter prescaler the tim clock source can be one of the seven presca ler outputs. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tim status and control register select the tim clock source. 18.3.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture chann el, the tim latches the contents of the tim counter into the tim channel registers, tchxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. 18.3.3 output compare with the output compare function, the tim can generat e a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tim can set, clear, or toggle the ch annel pin. output compares can generate tim cpu interrupt requests. 18.3.3.1 unbuffered output compare any output compare channel can generate unbuffer ed output compare pulses as described in 18.3.3 output compare . the pulses are unbuffered because changing t he output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel regist ers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim overfl ow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchronize unbuffer ed changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt rout ine has until the end of the counter overflow period to write the new value. $0029 timer channel 1 register high (t1ch1h) see page 199. read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002a timer channel 1 register low (t1ch1l) see page 199. read: bit 7654321bit 0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented figure 18-3. tim i/o register summary (sheet 2 of 2) functional description mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 189 when changing to a larger output compare value, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 18.3.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of t he linked pair alternately control the output. setting the ms0b bit in tim channel 0 status and control register (tsc 0) links channel 0 and channel 1. the output compare value in the tim channel 0 register s initially controls the output on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the output after the tim overflows. at each subsequent ov erflow, the tim channel registers (0 or 1) that control the output are the ones written to last. ts c0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. note in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 18.3.4 pulse widt h modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo regi sters determines the period of the pwm signal. the channel pin toggles when the counter reaches the valu e in the tim counter modulo registers. the time between overflows is the period of the pwm signal. as figure 18-4 shows, the output compare value in the tim channel registers determines the pulse width of the pwm signal. the time between overflow and out put compare is the pulse width. program the tim to clear the channel pin on output compare if the stat e of the pwm pulse is logic 1. program the tim to set the pin if the state of the pwm pulse is logic 0. figure 18-4. pwm period and pulse width tchx period pulse width overflow overflow overflow output compare output compare output compare timer interface module (tim) mc68hc908lb8 data sheet, rev. 0 190 freescale semiconductor the value in the tim counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000. see 18.8.1 tim status and control register . the value in the tim channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim channel registers produces a duty cycle of 128/256 or 50%. 18.3.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 18.3.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new va lue prevents any compare during that pwm period. also, using a tim overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchronize unbuffer ed changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 18.3.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc 0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse width are the ones written to last. tsc0 controls and monitors the buffered pwm function, and tim channel 1 status and control register (tsc1) is unused. interrupts mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 191 note in buffered pwm signal generation, do not write new pulse width values to the currently active channel regist ers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 18.3.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by setting the tim stop bit, tstop. b. reset the tim counter and prescaler by setting the tim reset bit, trst. 2. in the tim counter modulo registers (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (tchxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode se lect bits, msxb:msxa. see table 18-2 . b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. see table 18-2 . note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control register (tsc), clear the tim stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim channel 0 registers (tch0h:tch0l) initially control the bu ffered pwm output. tim status control register 0 (tscr0) controls and monitors the pwm signal from the linked channels. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. see 18.8.4 tim channel status and control registers . 18.4 interrupts the following tim sources can generate interrupt requests: timer interface module (tim) mc68hc908lb8 data sheet, rev. 0 192 freescale semiconductor tim overflow flag (tof) ? the tof bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim status and control register. tim channel flags (ch1f:ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interr upt requests are controlled by the channel x interrupt enable bit, chxie. channel x tim cpu interrupt requests are enabled when chxie = 1. chxf and chxie are in the tim channel x status and control register. 18.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 18.5.1 wait mode the tim remains active after the execution of a wait instruction. in wait mode, the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, r educe power consumption by stopping the tim before executing the wait instruction. 18.5.2 stop mode the tim is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. 18.6 tim during break interrupts a break interrupt stops the tim counter. the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bits during the break state. see 17.7.3 break flag control register . to allow software to clear status bits during a break in terrupt, write a 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a 0 to the bcfe bit. with bcfe at 0 (its default state), software can read and write i/o registers during the brea k state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if so ftware does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at 0. after the break, doing the second step clears the status bit. 18.7 i/o signals port b shares its pins with the tim. only tch0 is available on a port pin. it is programmable independently as an input capture pin or an output compare pin. t ch0 can be configured as buffered output compare or buffered pwm pins. i/o registers mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 193 18.8 i/o registers these i/o registers control and monitor operation of the tim: tim status and control register (tsc) tim counter registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and control registers (tsc0 and tsc1) tim channel registers (tch0h:tch0l, tch1h:tch1l) 18.8.1 tim status and control register the tim status and control register (tsc): enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock tof ? tim overflow flag bit this read/write flag is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and then writing a 0 to tof. if another tim overflow occurs before the clearing sequence is complete, then writing 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears th e tof bit. writing a 1 to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bit enables tim overflow interrupt s when the tof bit becom es set. reset clears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled tstop ? tim stop bit this read/write bit stops the tim counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active address: $0020 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 18-5. tim status and control register (tsc) timer interface module (tim) mc68hc908lb8 data sheet, rev. 0 194 freescale semiconductor note do not set the tstop bit before entering wait mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tim counter is reset and always reads as 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the tim counter as table 18-1 shows. reset clears the ps[2:0] bits. 18.8.2 tim counter registers the two read-only tim counter registers contain the high and low bytes of the value in the tim counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. table 18-1. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock address: $0021 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 = unimplemented figure 18-6. tim counter registers high (tcnth) address: $0022 figure 18-7. tim counter registers low (tcntl) i/o registers mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 195 note if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latched during the break. 18.8.3 tim counter modulo registers the read/write tim modulo register s contain the modulo value for the tim counter. when the tim counter reaches the modulo value, the overflow flag (tof ) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the hi gh byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim counter modulo registers. note reset the tim counter before writing to the tim counter modulo registers. 18.8.4 tim channel status and control registers each of the tim channel status and control registers: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger bit 7654321bit 0 read:bit 7654321bit 0 write: reset:00000000 = unimplemented address: $0023 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 figure 18-8. tim counter modulo register high (tmodh) address: $0024 bit 7654321bit 0 read: bit 7654321bit 0 write: reset:11111111 figure 18-9. tim counter modulo register low (tmodl) figure 18-7. tim counter registers low (tcntl) timer interface module (tim) mc68hc908lb8 data sheet, rev. 0 196 freescale semiconductor selects output toggling on tim overflow selects 0% and 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output com pare channel, chxf is set when the value in the tim counter registers matches the value in the tim channel x registers. when tim cpu interrupt requests are enabled (chx ie = 1), clear chxf by reading tim channel x status and control register with chxf set and then writing a 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x address: $0025 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 figure 18-10. tim channel 0 status and control register (tsc0) address: $0028 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 figure 18-11. tim channel 1 status and control register (tsc1) i/o registers mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 197 chxie ? channel x interrupt enable bit this read/write bit enables tim cpu interrupt service requests on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tim1 channel 0 and tim2 channel 0 status and control registers. setting ms0b disables the channel 1 status and cont rol register and reverts tch1 to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:a note before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tim status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/ write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port d, and pin ptdx/tchx is available as a gener al-purpose i/o pin. table 18-2 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. note before enabling a tim channel register for input capture operation, make sure that the ptd/tchx pin is stable for at least two bus clocks. timer interface module (tim) mc68hc908lb8 data sheet, rev. 0 198 freescale semiconductor tovx ? toggle on overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tim counter overflows. when c hannel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim counter overflow. 0 = channel x pin does not toggle on tim counter overflow. note when tovx is set, a tim counter ov erflow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at 1, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 18-12 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 18-12. chxmax latency table 18-2. mode, edge, and level selection msxb:msxa elsxb:elsxa mode configuration x0 00 output preset pin under port control; initial output level high x1 00 pin under port control; initial output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 01 output compare or pwm toggle output on compare 01 10 clear output on compare 01 11 set output on compare 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare output overflow tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare i/o registers mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 199 18.8.5 tim channel registers these read/write registers contain the captured tim counter value of the input capture function or the output compare value of the output compare function. the state of the tim channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading th e high byte of the tim channel x registers (tchxh) inhibits input captures until the low byte (tchxl) is read. in output compare mode (msxb:msxa address: $0026 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 18-13. tim channel 0 register high (tch0h) address: $0027 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 18-14. tim channel 0 register low (tch0l) address: $0029 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 18-15. tim channel 1 register high (tch1h) address: $002a bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 18-16. tim channel 1 register low (tch1l) timer interface module (tim) mc68hc908lb8 data sheet, rev. 0 200 freescale semiconductor mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 201 chapter 19 development support 19.1 introduction this section describes the break module, the moni tor read-only memory (mon), and the monitor mode entry methods. 19.2 break module (brk) the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. features of the break module include: accessible input/output (i/o) registers during the break interrupt central processor unit (cpu) generated break interrupts software-generated break interrupts computer operating properly (cop ) disabling during break interrupts 19.2.1 functional description when the internal address bus matches the value writt en in the break address registers, the break module issues a breakpoint signal (bkpt ) to the system integration module (sim). the sim then causes the cpu to load the instruction register with a software interrupt instruction (swi) after completion of the current cpu instruction. the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu generated address (the address in the program counter) matches the contents of the break address registers. software writes a 1 to the brka bit in the break status and control register. when a cpu generated address matches the contents of t he break address registers, the break interrupt begins after the cpu completes its current instruction. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the microcontroller unit (mcu) to normal operation. figure 19-1 shows the structure of the break module. figure 19-2 provides a summary of the i/o registers. development support mc68hc908lb8 data sheet, rev. 0 202 freescale semiconductor figure 19-1. break module block diagram 19.2.1.1 flag protection during break interrupts the system integration module (sim) controls whether or not module status bits can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see 17.7.3 break flag control register and the break interrupts subsection for each module. addr.register name bit 7654321bit 0 $fe00 break status register (bsr) see page 205. read: rrrrrr sbsw r write: note (1) reset: 0 $fe02 break auxiliary register (brkar) see page 204. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $fe03 break flag control register (bfcr) see page 205. read: bcferrrrrrr write: reset: 0 $fe09 break address high register (brkh) see page 204. read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $fe0a break address low register (brkl) see page 204. read: bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 write: reset:00000000 $fe0b break status and control register (brkscr) see page 203. read: brke brka 000000 write: reset:00000000 1. writing a 0 clears sbsw. = unimplemented r = reserved figure 19-2. break i/o register summary address bus[15:8] address bus[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high address bus[15:0] bkpt (to sim) break module (brk) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 203 19.2.1.2 cpu during break interrupts the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd ($fefc:$fefd in monitor mode) the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. 19.2.1.3 tim during break interrupts a break interrupt stops the timer counter. 19.2.1.4 cop during break interrupts the cop is disabled during a break interrupt with mo nitor mode when bdcop bit is set in break auxiliary register (brkar). 19.2.2 break module registers these registers control and monitor operation of the break module: break status and control register (brkscr) break address register high (brkh) break address register low (brkl) break status register (bsr) break flag control register (bfcr) 19.2.2.1 break status and control register the break status and control register (brkscr) contains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break address re gister matches. clear brke by writing a 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a 1 to brka generates a break interrupt. clear brka by writing a 0 to it before exiting the break routine. reset clears the brka bit. 1 = break address match 0 = no break address match address: $fe0b bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 19-3. break status and control register (brkscr) development support mc68hc908lb8 data sheet, rev. 0 204 freescale semiconductor 19.2.2.2 break address registers the break address registers (brkh and brkl) contai n the high and low bytes of the desired breakpoint address. reset clears the break address registers. 19.2.2.3 break auxiliary register the break auxiliary register (brkar) contains a bit that enables software to disable the cop while the mcu is in a state of break interrupt with monitor mode. bdcop ? break disable cop bit this read/write bit disables the cop during a break interrupt. reset clears the bdcop bit. 1 = cop disabled during break interrupt 0 = cop enabled during break interrupt. 19.2.2.4 break status register the break status register (bsr) contains a flag to i ndicate that a break caused an exit from wait mode. this register is only used in emulation mode. address: $fe09 bit 7654321bit 0 read: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 write: reset:00000000 figure 19-4. break address register high (brkh) address: $fe0a bit 7654321bit 0 read: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 write: reset:00000000 figure 19-5. break address register low (brkl) address: $fe02 bit 7654321bit 0 read:0000000 bdcop write: reset:00000000 = unimplemented figure 19-6. break auxiliary register (brkar) break module (brk) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 205 sbsw ? sim break stop/wait this status bit is useful in applications requiring a return to wait mode after exiting from a break interrupt. clear sbsw by writing a 0 to it. reset clears sbsw. 1 = wait mode was exited by break interrupt 0 = wait mode was not exited by break interrupt sbsw can be read within the break state swi routine. the user can modify t he return address on the stack by subtracting one from it. 19.2.2.5 break flag control register the break control register (bfcr) contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break 19.2.3 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. if enabled, the break module will remain enabled in wait and st op modes. however, since the internal address bus does not increment in these modes, a break interrupt will never be triggered. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset: 0 r = reserved 1. writing a 0 clears sbsw. figure 19-7. break status register (bsr) address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r = reserved figure 19-8. break flag control register (bfcr) development support mc68hc908lb8 data sheet, rev. 0 206 freescale semiconductor 19.3 monitor module (mon) note for monitor entry, v tst must be applied before v dd . this section describes the monitor module (mon) and the monitor mode entry methods. the monitor module allows complete testing of the microcontroller unit (mcu) through a single-wire interface with a host computer. monitor mode entry can be achieved without use of the higher test voltage, v tst , as long as vector addresses $fffe and $ffff are blank, thus reducing the hardware requirements for in-circuit programming. features include: normal user-mode pin functionality on most pins one pin dedicated to serial communication betwe en monitor read-only memory (rom) and host computer standard mark/space non-return-to-zero (nrz) communication with host computer execution of code in random-a ccess memory (ram) or flash flash memory security feature (1) flash memory programming interface standard communication baud rate (9600 @ 9.8304 mhz external oscillator or 4 mhz generated by internal oscillator) simple monitor mode entry using internal oscillator 350 bytes monitor rom code size ($fe20?$ff70) monitor mode entry without high voltage, v tst , if reset vector is blank ($fffe and $ffff contain $ff) normal monitor mode entry if high voltage is applied to irq 19.3.1 functional description figure 19-9 shows a simplified diagram of the monitor mode entry. the monitor module receives and execut es commands from a host computer. figure 19-10 , figure 19-11 , and figure 19-12 show example circuits used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute code downloaded into ram by a host computer wh ile most mcu pins retain normal operating mode functions. all communicati on between the host computer and the mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pullup resistor. table 19-1 shows the pin conditions for entering monitor mo de. as specified in the table, monitor mode may be entered after a power-on reset (por) and will allow communication at 9600 baud provided one of the following sets of conditions is met: if $fffe and $ffff does not contain $ff (programmed state): ? the external clock is 9.8304 mhz ?irq = v tst 1. no security feature is absolutely secu re. however, freescale semiconductor?s stra tegy is to make reading or copying the flash difficult for unauthorized users. monitor module (mon) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 207 note for entry into normal monitor mode, the irq pin must be at v tst before v dd is applied to the device. if $fffe and $ffff contain $ff (erased state): ? the external clock is 9.8304 mhz ?irq = v dd (this can be implemented through the internal irq pullup) if $fffe and $ffff contain $ff (erased state): ?irq = v ss (internal oscillator is select ed, no external clock required) ? the bus clock generated by the internal oscillator ? 4 mhz bus note location $ffc0 is programmed at the fa ctory with an osci llator trim value that will allow communication at 9600 baud. erasing this location may prevent communication with the device. development support mc68hc908lb8 data sheet, rev. 0 208 freescale semiconductor figure 19-9. simplified monitor mode entry flowchart monitor mode entry por reset pta1 = 1, pta4 = 0, and pta0 = 1? irq = v tst ? pta0 = 1, reset vector blank? yes no yes no forced monitor mode normal user mode normal monitor mode invalid user mode no no host sends 8 security bytes is reset por? yes yes yes no are all security bytes correct? no yes enable flash disable flash execute monitor code does reset occur? conditions from table 19-1 debugging and flash programming (if flash is enabled) monitor module (mon) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 209 figure 19-10. normal monitor mode circuit (external clock, with high voltage) the monitor code has been updated from previous ve rsions of the monitor code to allow enabling the internal oscillator to generate the internal cl ock. this addition, wh ich is enabled when irq is held low out of reset, is intended to support serial communication/ programming at 9600 baud in monitor mode by using the internal oscillator, and the internal oscillator user trim value osctrim (flash location $ffc0, if programmed) to generate the desired internal frequenc y (4.0 mhz). since this feature is enabled only when irq is held low out of reset, it cannot be used when the reset vector is programmed (i.e., the value is not $ffff) because entry into monitor mode in this case requires v tst on irq . enter monitor mode with pin configuration shown in figure 19-11 by pulling rst low and then high. the rising edge of rst latches monitor mode. once monitor mode is latched, the values on the specified pins can change. once out of reset, the mcu waits for the host to send eight security bytes (see 19.3.2 security ). after the security bytes, the mcu sends a break signal (10 consecut ive 0s) to the host, indicating that it is ready to receive a command. 9.8304 mhz clock + 10 k ? * v dd 10 k ? * rst (pta5) irq (ptc2) pta0 0.1 f osc1 (ptc0) 8 7 db9 2 3 5 16 15 2 6 10 9 v dd max232 v+ v? 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k ? pta1 pta4 v ss 0.1 f v dd 1 k ? 9.1 v c1+ c1? 5 4 1 f c2+ c2? + 3 1 1 f + 1 f v dd + 1 f v tst * value not critical v dd v dd 10 k ? * development support mc68hc908lb8 data sheet, rev. 0 210 freescale semiconductor figure 19-11. forced monitor mode circuit (external clock, no high voltage) figure 19-12. forced monitor mode circuit (internal clock, no high voltage) rst (pta5) irq (ptc2) pta0 osc1 (ptc0) 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 1 f max232 v+ v? v dd 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k ? n.c. pta1 n.c. pta4 v ss 0.1 f v dd 9.8304 mhz clock c1+ c1? 5 4 1 f c2+ c2? + 3 1 1 f + + + 1 f v dd 10 k ? * * value not critical n.c. v dd rst (pta5) irq (ptc2) pta0 10 k ? * osc1 (ptc0) n.c. 8 7 db9 2 3 5 16 15 2 6 10 9 v dd 1 f max232 c1+ c1? v+ v? 5 4 1 f c2+ c2? v dd 1 f + 1 2 3 4 5 6 74hc125 74hc125 10 k ? n.c. pta1 n.c. pta4 v ss 0.1 f v dd + 3 1 1 f + + + 1 f v dd * value not critical n.c. table 19-1. monitor mode signal requirements and options mode irq (ptc2) rst (pta5) reset vector serial communication mode selection cop communication speed comments pta0 pta1 pta4 external clock bus frequency baud rate ? x gnd x x x x x x x x reset condition normal monitor v tst v dd x 1 1 0 disabled 9.8304 mhz 2.4576 mhz 9600 provide external clock at osc1 forced monitor v dd v dd $ff (blank) 1 x x disabled 9.8304 mhz 2.4576 mhz 9600 provide external clock at osc1 gnd v dd $ff (blank) 1 x x disabled x 4 mhz 9600 internal clock is active user v dd or gnd v dd not $ff x x x enabled x x x mon08 function [pin no.] v tst [6] rst [4] ? com [8] mod0 [12] mod1 [10] ? osc1 [13] ?? 1. pta0 must have a pullup resistor to v dd in monitor mode. 2. communication speed in the t able is an example to obtain a baud rate of 9600. baud rate using external oscillator is bus fre quency / 256 and baud rate using internal oscillator is bus frequency / 417. 3. external clock is an 9.8304 mhz on osc1. 4. x = don?t care 5. mon08 pin refers to p&e microcomputer s ystems? mon08-cyclone 2 by 8-pin connector. nc 1 2 gnd nc 3 4 rst nc 5 6 irq nc 7 8 pta0 nc 9 10 pta4 nc 11 12 pta1 osc1 13 14 nc v dd 15 16 nc development support mc68hc908lb8 data sheet, rev. 0 212 freescale semiconductor if entering monitor mode without high voltage on irq (above condition set 2 or 3, where applied voltage is v dd or v ss ), then startup port pin requirements and conditions, (pta1/pta4) are not in effect. this is to reduce circuit requi rements when performing in-circuit programming. 19.3.1.1 normal monitor mode rst and osc1 functions will be active on the pt a5 and ptc0 pins, respectively, as long as v tst is applied to the irq pin. if the irq pin is lowered (no longer v tst ) then the chip will still be operating in monitor mode, but the pin functions will be determined by the settings in the configuration register when v tst was lowered. see chapter 5 configuration register (config) . when monitor mode is entered with v tst on irq , the computer operating properly (cop) is disabled as long as v tst is applied to irq . this condition states that as long as v tst is maintained on the irq pin after entering monitor mode, then the cop will be disabled. 19.3.1.2 forced monitor mode if the voltage applied to the irq1 is less than v tst , the mcu will come out of reset in user mode. however, when the reset vector is erased ($ffff), t he mcu is forced into monitor mode without requiring high voltage on the irq1 pin. once out of reset, the monitor code is initially executing off the internal clock at its default frequency. if irq is tied high (v dd ), all pins will default to regular input port functions except for pta0 and ptc0 which will operate as a serial communication port and osc1 input respectively (refer to figure 19-11 ). that will allow the clock to be driven fr om an external source through osc1 pin. if irq is tied low, all pins will default to regular input port function except for pta0 which will operate as serial communication port. refer to figure 19-12 . regardless of the state of the irq pin, it will not function as a port input pin in monitor mode. the cop module is disabled in forced monitor mode. note if the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial power-on reset (por). once the part has been programmed, the traditional method of applying a voltage, v tst , to irq must be used to enter monitor mode. 19.3.1.3 monitor vectors in monitor mode, the mcu uses different vectors for reset, swi (software interrupt), and break interrupt than those for user mode. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. table 19-2 summarizes the differences between user mode and monitor mode regarding vectors. table 19-2. mode difference modes functions reset vector high reset vector low break vector high break vector low swi vector high swi vector low user $fffe $ffff $fffc $fffd $fffc $fffd monitor $fefe $feff $fefc $fefd $fefc $fefd monitor module (mon) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 213 19.3.1.4 data format communication with the monitor module is in standard non-return-to-zero (nrz) mark/space data format. transmit and receive baud rates must be identical. figure 19-13. monitor data format 19.3.1.5 break signal a start bit (0) followed by nine 0 bits is a break signal . when the monitor receives a break signal, it drives the pta0 pin high for the duration of two bits and then echoes back the break signal. figure 19-14. break transaction 19.3.1.6 baud rate the communication baud rate is controlled by the exter nal clock frequency or internal oscillator frequency. table 19-1 has the external frequency required to achieve a standard baud rate of 9600 bps. the effective baud rate is the bus frequency divided by 256 for the ex ternal oscillator and divided by 417 for the internal oscillator. if a crystal is used as the source, be aware of the upper frequency limit that the mcu can operate. 19.3.1.7 commands the monitor module firmware uses these commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) the monitor module firmware echoes each received byte back to the pt a0 pin for error checking. an 11-bit delay at the end of each command allows t he host to send a break character to cancel the command. a delay of two bit times occurs before each echo and before read, iread, or readsp data is returned. the data returned by a read command appears after the echo of the last byte of the command. note wait one bit time after each echo before sending the next byte. bit 5 start bit bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 7 bit 0 bit 6 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit approximately 2 bits delay before zero echo development support mc68hc908lb8 data sheet, rev. 0 214 freescale semiconductor figure 19-15. read transaction figure 19-16. write transaction read read echo from host address high address high address low address low data return 13, 2 11 4 4 notes: 2 = data return delay, approximately 2 bit times 3 = cancel command delay, 11 bit times 4 = wait 1 bit time before sending next byte. 44 1 = echo delay, approximately 2 bit times write write echo from host address high address high address low address low data data notes: 2 = cancel command delay, 11 bit times 3 = wait 1 bit time before sending next byte. 11 3 11 3 3 32, 3 1 = echo delay, approximately 2 bit times monitor module (mon) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 215 a brief description of each monitor mode command is given in table 19-3 through table 19-8 . table 19-3. read (read memory) command description read byte from memory operand 2-byte address in high-byte:low-byte order data returned returns contents of specified address opcode $4a command sequence table 19-4. write (write memory) command description write byte to memory operand 2-byte address in high-byte:low-byte order; low byte followed by data byte data returned none opcode $49 command sequence table 19-5. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence read read echo sent to monitor address high address high address low data return address low write write echo from host address high address high address low address low data data iread iread echo from host data return data development support mc68hc908lb8 data sheet, rev. 0 216 freescale semiconductor a sequence of iread or iwrite commands can acce ss a block of memory sequentially over the full 64-kbyte memory map. table 19-6. iwrite (indexed write) command description write to last address accessed + 1 operand single data byte data returned none opcode $19 command sequence table 19-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns incremented stack pointer value (sp + 1) in high-byte:low-byte order opcode $0c command sequence table 19-8. run (run user program) command description executes pulh and rti instructions operand none data returned none opcode $28 command sequence iwrite iwrite echo from host data data readsp readsp echo from host sp return sp high low run run echo from host monitor module (mon) mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 217 the mcu executes the swi and pshh instructions when it enters monitor mode. the run command tells the mcu to execute the pulh and rti instru ctions. before sending th e run command, the host can modify the stacked cpu registers to prepare to run the host program. the readsp command returns the incremented stack pointer value, sp + 1. the high and low bytes of the program counter are at addresses sp + 5 and sp + 6. figure 19-17. stack pointer at monitor mode entry 19.3.2 security a security feature discourages unauthorized reading of flash locations while in monitor mode. the host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. locations $fff6?$fffd contain user-defined data. note do not leave locations $fff6?$fffd bl ank. for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the powe r-on reset for the host to send the eight security bytes on pin pta0. if the received bytes match those at locations $fff6?$fffd, the host bypasses the security feature and can read all flash locations and execute code from flash. security remains bypassed until a power-on reset occurs. if the reset wa s not a power-on reset, security remains bypassed and security code entry is not required. see figure 19-18 . upon power-on reset, if the received bytes of the security code do not match the data at locations $fff6?$fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading a flash location returns an invalid value and trying to execute code from flash causes an illegal address reset. after receiving the eight secu rity bytes from the host, the mcu transmits a break character, signifying that it is ready to receive a command. note the mcu does not transmit a break char acter until after the host sends the eight security bytes. condition code register accumulator low byte of index register high byte of program counter low byte of program counter sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp sp + 6 high byte of index register sp + 7 development support mc68hc908lb8 data sheet, rev. 0 218 freescale semiconductor figure 19-18. monitor mode entry timing to determine whether the security code entered is correct, check to see if bit 6 of ram address $80 is set. if it is, then the correct security code has been entered and flash can be accessed. if the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. after failing the securi ty sequence, the flash module can also be mass erased by executing an erase routine that was downl oaded into internal ram. the mass erase operation clears the security code locations so that all eight security bytes become $ff (blank). byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pa0 rst v dd 4096 + 32 busclkx4 cycles 5 1 4 1 1 2 1 break notes: 2 = data return delay, approximately 2 bit times 4 = wait 1 bit time before sending next byte 4 from host from mcu 1 = echo delay, approximately 2 bit times 5 = wait until the monitor rom runs mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 219 chapter 20 electrical specifications 20.1 introduction this section contains electrical and timing specifications. 20.2 absolute maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. note this device is not guaranteed to operate properly at the maximum ratings. refer to 20.5 5.0-volt electrical characteristics and for guaranteed operating conditions. note this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields ; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss electrical specifications mc68hc908lb8 data sheet, rev. 0 220 freescale semiconductor 20.3 functional operating range 20.4 thermal characteristics 20.5 5.0-volt electrical characteristics characteristic symbol value unit operating temperature range t a ?40 to +125 ) w constant (2) 2. k is a constant unique to the device. k can be determined for a known t a and measured p d . with this value of k, p d and t j can be determined for any value of t a . k p d / 5.0-volt control timing mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 221 20.6 5.0-volt control timing v dd supply current run (3) wait (4) stop (5) ?40 ? electrical specifications mc68hc908lb8 data sheet, rev. 0 222 freescale semiconductor figure 20-1. rst and irq timing 20.7 oscillator characteristics notes: 1. v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd unless otherwise noted. 2. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. 3. minimum pulse width is for guaranteed interrupt. it is possible for a smaller pulse width to be recognized. characteristic symbol min typ max unit internal oscillator frequency (factory trimmed) f intclk 15.2 16 (1) notes: 1. characterization shows that 3.5% could be achieved from -40 to 85 c. 16.8 mhz crystal frequency, xtalclk f oscxclk 8?24mhz external rc oscillator frequency, rcclk f rcclk 2?12mhz external clock reference frequency (2) 2. no more than 10% duty cycle deviation from 50%. f oscxclk dc ? 32 mhz crystal load capacitance (3) 3. consult crystal vendor data sheet. c l ?20?pf crystal fixed capacitance (2) c 1 ? 2 x c l ?? crystal tuning capacitance (2) c 2 ? 2 x c l ?? feedback bias resistor r b ?10?m ? rst irq t rl t ilih t ilil 5.0-volt adc characteristics mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 223 figure 20-2. rc versus frequency (5 volts @ 25c) 20.8 5.0-volt adc characteristics characteristic symbol min max unit comments supply voltage v ddad 4.5 (v dd min) 5.5 (v dd max) v? input voltages v adin v ss v dd v? resolution b ad 88bits ? absolute accuracy a ad ? 0 0 1020304050 14 12 10 8 6 4 2 resistor, r ext (k ? ) rc frequency, f rcclk (mhz) r ext osc1 v dd mcu 5 v @ 25c electrical specifications mc68hc908lb8 data sheet, rev. 0 224 freescale semiconductor 20.9 op amp parameters (measured over -40 ? ? ? ? ? ? ? ? ? comparator parameters mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 225 20.10 comparator parameters 20.11 timer interface module characteristics (measured over -40 ? ? ? ? ? electrical specifications mc68hc908lb8 data sheet, rev. 0 226 freescale semiconductor figure 20-3. input capture timing 20.12 memory characteristics characteristic symbol min typ max unit ram data retention voltage v rdr 1.3 ? ? v flash program bus clock frequency ? 1 ? ? mhz flash read bus clock frequency f read (1) 0?8 mhz flash page erase time <1 k cycles >1 k cycles t erase (2) 0.9 3.6 1 4 1.1 5.5 ms flash mass erase time t merase (3) 4??ms flash pgm/erase to hven setup time t nvs 10 ? ? input capture rising edge input capture falling edge input capture both edges t th t tl t tltl t tltl t tltl t tl t th memory characteristics mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 227 notes: 1. f read is defined as the frequency range for which the flash memory can be read. 2. if the page erase time is longer than t erase (min), there is no erase disturb, bu t it reduces the endurance of the flash memory. 3. if the mass erase time is longer than t merase (min), there is no erase disturb, but it reduces the endurance of the flash memory. 4. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clear- ing hven to 0. 5. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog x electrical specifications mc68hc908lb8 data sheet, rev. 0 228 freescale semiconductor mc68hc908lb8 data sheet, rev. 0 freescale semiconductor 229 chapter 21 ordering information and mechanical specifications 21.1 introduction this section provides ordering information for the mc68hc908gz8 along with the dimensions for: 20-pin small outline intergrated circuit (soic) ? case 751d 20-pin plastic dual in-line package (pdip) ? case 738 the following figures show the latest package drawings at the time of th is publication. to make sure that you have the latest package specif ications, contact your local frees cale semiconductor sales office. 21.2 mc order numbers table 21-1. mc order numbers mc order number operating temperature range package mc68hc908lb8cdwe ?40c to +85c 20-pin small outline integrated circuit (soic) mc68hc908lb8vdwe ?40c to +105c mc68hc908lb8mdwe ?40c to +125c mc68hc908lb8cpe ?40c to +85c 20-pin plastic dual in-line package (pdip) MC68HC908LB8VPE ?40c to +105c mc68hc908lb8mpe ?40c to +125c temperature and package designators: c = ?40c to +85c v = ?40c to +105c m = ?40c to +125c dw = small outline integrated circuit package (soic) e = leadfree p = plastic dual in-line package (pdip) ordering information and mechanical specifications mc68hc908lb8 data sheet, rev. 0 230 freescale semiconductor 21.3 20-pin small outlin e integrated circuit (soic) package ? case #751d 21.4 20-pin plastic dual in-l ine package (pdip) ? case #738 ! " # ! $ -a- -b- p 10 pl 110 11 20 -t- d 20 pl k c r x 45 ! ! g 18 pl f j # $ "# $ $# -a- c k n e gf d 20 pl j 20 pl l m -t- 110 11 20 ! ! b how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical ex perts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the arm powered logo is a registered trademark of arm limited. arm7tdmi-s is a trademark of arm limited. java and all other java-based marks are trademarks or registered trademarks of sun microsystems, inc. in the u.s. and other countries. the bluetooth trademarks are owned by their proprietor and used by freescale semiconductor, inc. under license. ? freescale semiconductor, inc. 2005. all rights reserved. mc68hc908lb8 rev. 0 2/2005 |
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